Vlsi Technology, Inc.

Koninklijke Philips Corporation N.V.

James J Jirgal

David R Evoy

Gary A Walker

Franklyn H Story

Subramanian S Meiyappan

Walter H Potts

Rishi Nalubola

Roger W Luce

Duane F Krolski

A computer system is provided with a memory management unit (MMU) utilizing a translation look-aside buffer (TLB) arrangement. The computer system includes a bus, a unified cache memory, a main memory, a processor, and a memory controller. The TLB is configured for storing code and/or data. The main memory is coupled to the bus. The main memory contains descriptor tables for mapping virtual-to-physical address translations within a virtual memory system. The processor is coupled to the bus and the unified cache memory. The processor is configured to communicate and sequentially move through the main memory to retrieve a line of information from the main memory for storage in the unified cache memory. The cache is configured for storing the most recently retrieved code and data from main memory. The memory controller is coupled between the bus and the main memory. The memory controller is operative to enable the processor to retrieve the information in the form of descriptor page table entries for the translation lookaside buffer (TLB), or code and/or data for the unified cache memory. A method is also provided.

Background fetching of translation lookaside buffer (TLB) entries

A bus bridge device for enabling communication between a first device and a second device, wherein the first device is based on advanced microprocessor bus advanced system bus (ASB) protocol and the second device is based on peripheral component interconnect (PCI) protocol. The bus bridge device includes an ASB protocol interface coupled to the ASB protocol device, and the ASB protocol interface is adapted to transmit a response to and receive a transaction from the ASB protocol device. The bus bridge device also includes a PCI protocol interface coupled to the PCI protocol device, and the PCI protocol interface is adapted to transmit a transaction to and receive a response from the PCI protocol device. The ASB protocol interface is coupled to the PCI protocol interface. The ASB protocol interface is adapted to forward the transaction from the ASB protocol device to the PCI protocol interface, and the PCI protocol interface is adapted to forward the response from the PCI protocol device to the ASB protocol interface.

Bus bridge device for advanced microcontroller bus architecture (AMBA) advanced system bus (ASB) protocol

The present invention is drawn to a computer implemented method and system for synchronously driving slave responses onto an ASB (advanced system bus) bus. On the one hand, in response to a read transfer from a ASB master, an ASB slave predicts the read transfer to be intended for a device attached to the ASB slave if the device is ready to return read data. On the other hand, in response to a write transfer from the ASB master, the ASB slave predicts the write transfer to be intended for the device attached to the ASB slave. In both scenarios, a device select signal (Dsel) is utilized to validate these two predictions. That is, the read slave response driven by the ASB slave does not enter the ASB bus when the device select signal does not select the ASB slave. Also, the write slave response driven by the ASB slave does not enter the ASB bus when the device select signal does not select the ASB slave. In so doing, when these two predictions are valid, the ASB slave can synchronously drive appropriate slave responses onto the ASB bus without inserting wait states. Moreover, when these two predictions are not valid, wrong slave responses are prevented from entering the ASB bus.

Predictive mechanism for ASB slave responses

An apparatus is provided for interfacing a processor with a bus of a computer system wherein the processor performs burst read operations in both a sequential and a non-sequential manner and the bus is incapable of supporting burst operations that are non-sequential. The apparatus includes an interface adaptor circuit that is coupled between the processor and the bus. The interface adaptor circuit is operative as a burst order translator between the processor and the bus, and has a bridge configured to connect together the processor and the bus. The bridge is operative to translate processor burst operations into operations supported by the bus. The bridge has a processor interface coupled between the processor and the interface adaptor circuit and a bus interface coupled between the bus and the interface adaptor circuit. The bridge is operative to enable compatibility between the processor interface and the bus interface such that non-sequential burst access from the processor is supported and deliverable as sequential burst access to the bus.

Apparatus and method for interfacing a non-sequential 486 interface burst interface to a sequential ASB interface

A method and system for cache replacement among configurable cache sets. In one embodiment, the present invention identifies a cache location corresponding to uncached data received from main memory and determines a data type for the uncached data. The present invention then examines the cache location in at least one of the configurable cache sets which is configured for the data type of the uncached data. Provided that the cache location of at least one of the configurable cache sets is not occupied by valid data and that the same configurable cache set is configured for the data type of the uncached data, the present invention stores the uncached data into that configurable cache set at the cache location without displacing valid data therein. Provided that the cache location of each of the configurable cache sets which is configured for the data type of the uncached data is occupied by valid yet old data, the present invention replaces the old data stored in one of the configurable cache sets at the cache location with the uncached data. This embodiment of the present invention thus provides a method for cache replacement among configurable cache sets.

Method and system for cache replacement among configurable cache sets

The present invention relates to a system and method for supporting DMA I/O devices. A PCI-PCI bridge is provided to support DMA I/O devices on the PCI bus. Through the use of two signal lines and a serial link, DMA transfers may be accomplished over the PCI bus. A PCI-ISA dock bridge is also provided to allow the system to support DMA I/O devices and ISA masters (i.e., any device including DMA I/O devices on the ISA bus that generates ISA cycles) on the ISA bus.

System for supporting DMA I/O device using PCI bus and PCI-PCI bridge

A computer system having a multiplex address/data bus with a multiplex system controller and method therefor is disclosed which provides in a computer system having time shared use of a multiplex address/data bus to reduce the number of required pins for devices within the computer system, a CPU having at least one address bus, at least one data bus, at least one memory input/output, and at least one CPU control bus coupled thereto for sending and receiving information. In addition, this system includes at least one memory input/output device coupled to a first portion of the address bus for sending and receiving at least one of address information and data information, at least one input/output only device coupled to a second portion of the address bus for sending and receiving at least one of address information and data information, and a multiplex system controller coupled to the CPU and the address bus and having a multiplex control bus coupled to both the memory input/output device and to the input/output only device for taking control of the address bus from the CPU.

Multiplex address/data bus with multiplex system controller and method

A system for altering a clock frequency to a logic controlling device that controls logic which runs at a fixed frequency slower than a frequency of a computer system running the logic. The system speeds up the clock signal to a logic controller when the logic controller is arbitrating between different operational requests. When the logic controller acknowledges a specific operational request, the clock controller immediately slows the clock signal down in order to allow a command strobe length that the logic device executing a specific operation request requires.

System and method for altering the clock frequency to a logic controller

The present invention relates to an apparatus and method for supporting DMA I/O devices on a PCI bus. A DMA I/O device is coupled to a DMA controller via a serial link and two signal lines. The serial link is used by the DMA I/O device to request a DMA transfer. When the DMA controller receives the serialized DMA request, it sends a signal to an arbiter and waits for the PCI bus to be granted to the DMA controller for use during the DMA transfer. When granted the PCI bus, the DMA controller signals the DMA I/O device. The DMA I/O device asserts a signal in response to the one asserted by the DMA controller. The DMA controller recognizes the signal asserted by the DMA I/O device and continues with the DMA transfer. The transfer continues for as long as the DMA I/O device continues to assert the signal or for as long as the DMA controller is programmed.

Signalling system and method for allowing a direct memory access (DMA)

An event driven power management control system. The event driven power management control system is compatible with existing CPU power management control units which only monitor CPU activity. The event driven power management control system is able to modify a STPCLK# signal asserted by the CPU power management control unit if external or internal events in the computer system require the CPU to run at full speed in order to service the break event.

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Chandler, AZ, United States of America

James J Jirgal