Intel Corporation

James J Grealish

Lakshminarayana Pappu

David W Grawrock

Bruce Querbach

Tieyu Zheng

Keshavan K Tiruvallur

Mark B Trobough

Chinna B Prudvi

Hermann Gartler

Vui Yong Liew

Ashok N Kabadi

Samie B Samaan

Keith A Drescher

Jay Joseph Nejedlo

Mukesh Kataria

George L Arrigotti

Lyle E Cool

Russell J Wunderlich

Brian Meyer

Abhijit Davare

Priyadarsan Patra

William Penner

Rahima K Mohammed

Ridvan A Sahan

Wee Hoo Cheah

Arun R Ramadorai

Kapila B Udawatta

Yuen Tat Lee

John L Baudrexl

Eric T Fought

Kip C Killpack

Loren James McConnell

Kyle Markley

Christian E Iovin

Padmakumar Gopal

Travis K Goff

Sanjay S Salem

Evan J Halprin

David C Florey

Jiun Long Foo

Dave F Dubberke

Selvakumar Raja Gopal

Milo J Juenemann

Christopher J Koza

Kurt R Goldsmith

Neil Dobler

Nagib Z Hakim

Timothy S Storey

Yi Amy Xia

Edwin E Parks

A method and apparatus for platform component interconnect testing is disclosed. In one embodiment, an integrated circuit comprises: a plurality of interface circuitries, wherein each interface circuitry comprises a driver with adjustable pullup and pulldown resistances and having a driver output to output a driver voltage to a pad during test mode, and a comparator having a first input coupled to the driver output and a second input coupled to a voltage reference, the comparator being operable to generate a comparator output in response to comparing the driver voltage with the voltage reference; and analysis circuitry coupled to receive the comparator output, the analysis circuitry operable, during the test mode, to detect existence of a fault associated with a signal path coupled to the pad for each interface circuitry.

Platform component interconnect testing

Embodiments are generally directed to maintaining IO block operation in electronic systems for board testing. An embodiment of a system includes a processor; a power management block for the system; a plurality of IO (input/output) blocks; a read only memory for storage of firmware for the processor. The system is to provide support for a board-level test of the system including testing of one or more IO blocks of the plurality of IO blocks; and the firmware includes elements to stall a reset sequence of the system including the system branching to a mode that maintains power to the one or more IO blocks.

Maintaining IO block operation in electronic systems for board testing

Embodiments are generally directed to board level leakage testing for a memory interface. An embodiment of an apparatus includes multiple logic cells for testing of a memory interface, each logic cell being connected to an interconnect for a respective memory element. Each logic cell includes a driver to drive a signal onto the interconnect with the respective memory element, an element to generate a value for the logic cell by comparing a signal with a reference voltage, a flip-flop to capture a cell value for the logic cell, and a drive control element to control the value driven on the interconnect by the driver. The apparatus further includes a processor to identify failure conditions based at least in part on testing using the logic cells.

Board level leakage testing for memory interface

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

A boundary scan technique to generate toggling waveform such as a square wave signal to perform structural testing is disclosed. An instr_extesttoggle command is provided that enables IEEE 1149.1 boundary scan cell to selectively generate the toggling signal on the pre-specified output pads of the integrated circuit. The frequency of the toggling signal may be controlled by the JTAG clock signal and the frequency of the toggling signal may be independent of the length of the boundary scan chain. Such an approach circumvents provisioning test points on the interconnects of a printed circuit board.

Structural testing using boundary scan techniques

Various embodiments related to an integrated lid and test device for a socket, such as a land grid array (LGA) socket, that functions as a lid, as a testing device, and/or as a pick and place lid. Specifically, the integrated lid may provide test capability, in manufacturing of the socket and/or a printed circuit board (PCB) such as a motherboard, onto which the socket is attached. Thus the integrated lid may allow for testing the socket and/or the PCB for correct assembly and connectivity without requiring removal of the integrated lid to insert a test device prior to testing, or removal of a test device and replacement of the lid after testing.

Socket lid and test device

A system and technique utilized to efficiently load data into a programmable electronic component connected to a circuit board through the use of automated test equipment. The system includes an automated testing equipment and a programmable electronic component coupled to data and address lines utilized by the programmable electronic component. For the first circuit board of a batch of multiple circuit boards, the reference programmable electronic component receives and stores data from an external source, prior to the data being loaded from the reference programmable electronic component into the programmable electronic component. Thereafter, further programming of the reference programmable electronic component is not required. Rather, the programmable electronic component coupled to any subsequent circuit boards requires only the reference programmable electronic component to copy its contents upon receiving address and control signals from the external source to perform such an operation.

System and method for programming programmable electronic components

Growing community of inventors

Beaverton, OR, United States of America

James J Grealish