International Business Machines Corporation

James J Engel

Peter Anton Habitz

Paul Steven Zuchowski

Jerry D Hayes

Susan K Lichtensteiger

Larry Wissel

William John Livingstone

Jeannie H Panner

Laura R Darden

Daniel Joseph Mainiero

Michael Timothy Trick

Paul J Sulva

A method and system of modeling power leakage for a design comprises providing one or more cell libraries comprising parameters for particular device characteristics and providing a module configured to determine of cell leakages of a device for a PVT corner. In determining the cell leakage, the module uses the device characteristics contained in the one or more cell libraries, in combination with one or more components at a PVT for a predetermined application and an amount of devices in a leakage path (Fckt) and a leakage distribution (Fchip). There is no need to recharacterize the one or more cell libraries.

Method and system of modeling leakage

The invention presents a method of accommodating for across chip line variation (ACLV) and/or changing static timing of an integrated circuit design. The invention first establishes a circuit design having initial timing requirements and an initial voltage supply and also establishes a relationship between gate timing variations caused by voltage supply changes and gate timing variations caused by manufacturing processing changes. Then, according to the customer's orders that change the initial timing requirements to revised timing requirements, the invention changes the initial voltage supply to a revised voltage supply to accommodate the revised timing requirements (and ACLV if desired) based on the relationship between voltage limits and transistor delay. This process of changing the initial voltage supply does not alter the circuit design.

Variable sigma adjust methodology for static timing

A computerized tool or method that calculates the capacitance and resistance of each global wire on the chip, one wire at a time. The invention steps along a track containing a wire segment, grid point by grid point, calculating the resistance and capacitance at that point. At each grid point it searches the neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire. The method delivers capacitance and resistance values for each process condition for a grid unit length of wire, given the wire type and 3 dimensional environment of the wire segment. The capacitance and resistance at a grid point along the wire are generally determined by one table lookup for wire types based on the surrounding environment. These values are added along wire segments to deliver accurate 3 dimensional capacitances and resistances. The invention can also provide for wires and spaces of various types and widths not provided for in the tables and for calculation of net to net coupling capacitances.

Three dimensional track-based parasitic extraction

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Cambridge, VT, United States of America

James J Engel