Infineon Technologies Ag

Infineon Technologies North America Corp.

James J Dietz

David SuitWai Ma

Bing Ren

Tao Wang

George William Alexander

Thoai Thai Le

Daivid SuitWai Ma

Petros Negussu

A multi-chip package comprising at least a first die and a second die, wherein each die comprises an integrated circuit (IC) disposed thereon. Each of the first die and the second die comprise a plurality of contact pads coupled with the respective IC. The contact pads on the first IC comprise a first mode pad coupled to a first device formed on the first die, and the contact pads on the second IC comprise a second mode pad coupled to a second device formed on the second die. The first mode pad is coupled to a first potential and causes the first device to operate in a first mode. The second mode pad is coupled to a second potential and causes the second device to operate in a second mode. The first and second mode are selected based on the relative position of the first and second die.

Differential chip performance within a multi-chip package

A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies. The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.

System and method for testing one or more dies on a semiconductor wafer

A memory includes input/output paths and electrical leads. Each of the input/output paths are coupled to separate electrical leads. The memory is configured to operate in a test architecture and an operating architecture. In the test architecture, logic enables a greatest number of input/output paths. In the operating architecture, the memory enables the same or fewer input/output paths. The method of selecting a configuration includes establishing an operating and a test architecture and testing the memory in its greater input/output configuration.

Integrated circuit in a maximum input/output configuration

A testing system or method compares read data from one or more dies in a semiconductor wafer with the original data written onto the one or more dies The testing system includes one or more write registers connected to one or more dies on the semiconductor wafer. One or more comparators are connected to the dies and the write registers. The comparator generates a result in response to the original data and the read data.

A semiconductor wafer testing system tests one or more die clusters on a semiconductor wafer, using a test circuit to test multiple sections or areas of each die in parallel. The semiconductor wafer testing system has a buffer connected to the die cluster via the test circuit. The buffer writes test data onto a section of each die in the die cluster. The buffer reads test data from the section of each die in the die cluster.

Semiconductor wafer testing system

An apparatus for mounting a semiconductor device to a circuit board for testing is disclosed. The semiconductor device includes semiconductor circuitry and leads to connect the semiconductor circuitry to the circuit board. Additionally, the semiconductor device is decapped so that at least a portion of the semiconductor circuitry is exposed. The apparatus includes a frame and a fastener. The frame is adapted to mate with the semiconductor device, and forms an opening for accessing the semiconductor circuitry and an edge surface for receiving the semiconductor device. The fastener is connected with the frame for removably connecting the frame to the circuit board. By using a frame instead of a socket, the distance to the semiconductor device once the device is mounted to the circuit board, and particularly the top side of the semiconductor device, can be reduced so that the device may be tested using a probe.

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Durham, NC, United States of America

James J Dietz