International Business Machines Corporation

James Ira Brookhouser

John Michael Borkenhagen

Richard James Eickemeyer

Sheldon Bernard Levenstein

Andrew Henry Wottreng

Duane Arlyn Averill

A method and apparatus is disclosed to improve the transfer of data from a transition cache to a level one data cache wherein the transition cache is receiving data from a plurality of data devices. In particular, logic is implemented via a line fill sequencer that allows for the interleaving of data packets being written into the level one data cache. Thus, data packets originating from a 'fast' level two data cache can be interleaved with data originating from a 'slow' system bus to avoid delays to the data originating from the level two data cache. Accordingly, the cache miss sequencer tracking the data from the level two data cache can be retired sooner.

Method and apparatus to interleave level 1 data cache line fill data

The data processing system includes a plurality of execution units forming a plurality of processing pipelines. The plurality of processing pipelines process instructions and include a storage pipeline. The data processing system further includes an instruction unit and a storage control unit. The instruction unit outputs instructions to the plurality of execution units, and controls execution of multiple threads by the plurality of execution units. If an instruction for a first thread in the storage pipeline experiences a cache miss and the instruction unit decides to switch threads, the instruction unit begins processing a second thread. The instruction unit also issues a data request to the storage control unit to obtain the missing data. During processing of the second thread, unused slots will appear in the storage pipeline because it is not possible to always dispatch instructions to completely keep the pipelines filled. After the requested data returns from higher level memory, the storage control unit will dispatch the instruction from the first thread having received the cache miss to an unused slot in the storage pipeline. Consequently, this instruction from the first thread will be processed along with the instructions from the second thread.

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Rochester, MN, United States of America

James Ira Brookhouser