Qualcomm Incorporated

Motorola Corporation

James Ian Jaffee

Gurkanwal Singh Sahota

Seyfollah Seyfollahi Bazarjani

Mustafa Keskin

Michael J DeLuca

Ernest Tadashi Ozaki

Chiewcharn Narathong

Jeremy Darren Dunworth

Nigel P Cook

Haim Mendel Weissman

Virginia Walker Keating

Aleksandar Miodrag Tasic

Peter J Shah

Cheng-Han Wang

Gary John Ballantyne

Louis Dominic Oliveira

Charles James Persico

Charles W Mooney

Steven C Ciccarelli

Prasad Srinivasa Siva Gudem

Brett Christopher Walker

Ojas Choksi

Christian Holenstein

Hong Sun Kim

Thomas J Rollins

Rinat Burdo

Anosh Bomi Davierwalla

Michael John Mangan

Klaas Van Zalinge

Miles A Kirby

Walter J Grandfield

George W Smoot

Steven M Mollenkopf

Rimon E Mansour

Derick Hugunin

Jungdong Park

Paul Brian Sheehy

Khalid Junaid Sidiqi

Puay Hoe Andrew See

Berke Cetinoneri

Jusung Kim

Sandor Szabo

Puay-Hoe Andrew See

Vincenzo Filip Andre Peluso

Runhua (Ray) Sun

Harry M Hunsicker

Ojas Mahendra Choksi

A user device determines whether a device connected to its headset jack is an audio accessory device. If the device connected to the headset jack is an audio accessory, the user device connects one or more pins of the headset jack to an audio codec. If the device plugged into the headset jack is not an audio accessory device, the user device connects one or more pins of the headset jack to alternate circuitry. The user device then determines, through the alternate circuitry, an electrical operating parameter requirement of the accessory device, and provides, from the alternate circuitry, the required operating parameter to the accessory device through the headset jack. The alternate circuitry may include an adjustable voltage regulator and/or an adjustable current regulator and the required operating parameter may be one or more of a voltage supply and a current supply.

Electronics interface for device headset jack

A nonlinear power supply generator is provided that nonlinearly changes a power supply voltage for a circuit during power up of the circuit to reduce high-frequency noise in an output signal from the circuit.

Nonlinear power supply ramping for pop-click noise reduction

An intermodulation distortion canceller for use in multi-carrier transmitters is disclosed. In an exemplary embodiment, an apparatus includes a first transmit chain that transmits a first RF signal, a second transmit chain that transmits a second RF signal, and a canceller that outputs a first leakage cancellation signal that is input to the second transmit chain, and outputs a second leakage cancellation signal that is input to the first transmit chain, the canceller generates the first and second leakage cancellation signals from the first and second RF signals or from first and second baseband signals used to generate the first and second RF signals.

Intermodulation distortion canceller for use in multi-carrier transmitters

Multiple-input multiple-output (MIMO) low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes a MIMO LNA having a plurality of gain circuits, a drive circuit, and a plurality of load circuits. The gain circuits receive at least one input radio frequency (RF) signal and provide at least one amplified RF signal. Each gain circuit receives and amplifies one input RF signal and provides one amplified RF signal when the gain circuit is enabled. The at least one input RF signal include transmissions sent on multiple carriers at different frequencies to the wireless device. The drive circuit receives the at least one amplified RF signal and provides at least one drive RF signal. The load circuits receive the at least one drive RF signal and provide at least one output RF signal.

Multiple-input multiple-output (MIMO) low noise amplifiers for carrier aggregation

Exemplary embodiments are directed to wireless power. A host device peripheral may comprise a wireless power charging apparatus, which may include transmit circuitry and at least one antenna coupled to the transmit circuitry. The at least one antenna may be configured to wirelessly transmit power within an associated near-field region. Additionally, the host device peripheral may be configured to couple to a host device.

Wireless power for charging devices

Certain aspects of the present disclosure provide methods and apparatus for performing quadrature combining and adjusting. One example circuit may include first through fourth mixing circuits. The first mixing circuit may multiply a radio frequency signal with a first local oscillating signal to generate a first frequency converted signal. The second mixing circuit may multiply a radio frequency (RF) signal with a second local oscillating signal, which may be about 90&#xb0; out of phase with the first local oscillating signal, to generate a second frequency converted signal. The third and fourth mixing circuits may multiply the RF signal with the second and first signals, respectively, to generate third and fourth frequency converted signals, respectively. A first combining circuit may combine the first and third frequency converted signals, and a second combining circuit may combine the second and fourth frequency converted signals.

Quadrature combining and adjusting

Techniques for cancelling DC offset are described. A DC offset cancellation circuit in a receiver cancels DC offsets caused by leaked LO (local oscillator) signals from a LO signal generator. The receiver first calibrates itself by using the DC offset cancellation circuit during a transmit mode. During the calibration, the DC offset cancellation circuit stores the DC offset voltage signal caused by the leaked LO signals. During a receiving mode when the receiver is receiving a signal, the receiver subtracts the stored DC offset voltage signal from the received signal to cancel the DC offsets caused by leaked LO signals.

DC offset cancellation circuit for a receiver

A phase modulator faithfully reproduces higher frequency modulation using an offset phase-locked loop (OPLL) without passing excessive noise through an increased bandwidth of the OPLL. A quadrature modulator modulates information from a baseband signal onto a passband IF signal and, after a limiter strips away amplitude variations, the OPLL reproduces the phase modulation on an RF signal. The OPLL introduces a group delay that does not vary linearly with the modulation frequency and that consequently causes distortion when uncompensated. A baseband filter filters the amplitude of the baseband signal and introduces a complementary group delay that compensates for the OPLL group delay and results in a combined group delay of the baseband filter, quadrature modulator, limiter and OPLL that remains substantially constant as modulation frequency varies. Compensating for the OPLL group delay reduces distortion and the spectral energy at offset frequencies from the carrier frequency of the RF signal.

Baseband compensation of an offset phase locked loop

Techniques for processing incoming signals conforming to a plurality of standards or communication formats with a single baseband receive section are disclosed. In one aspect, a plurality of analog processing components are adjusted in response to a format select signal, set according to one of a plurality of supported formats or standards. In another aspect, the operating mode of an A/D converter is tuned in response to the format select signal. In yet another aspect, the response characteristics of a jammer filter are tuned in response to the format select signal. In yet another aspect, the adjustment of the plurality of analog processing components is carried out by varying the frequency of a sample clock in response to the format select signal. Various other aspects are also presented. These aspects have the benefit of allowing a single baseband receive section to be deployed to process analog signals conforming to a plurality of communications standards or formats, in a power and area efficient manner.

Multi-standard baseband receiver

A wireless transceiver includes a transmitter having a harmonic rejection mixer and an RF output phase-locked loop in a two step up-conversion architecture, and a direct conversion receiver. The transmitter includes a local oscillator for producing a signal at a multiple of an intermediate frequency, a quadrature modulator harmonic rejection mixer responsive to the signal at the multiple of the intermediate frequency for modulating in-phase and quadrature-phase base-band signals to produce an intermediate frequency signal, a filter responsive to the intermediate frequency signal for producing a filtered intermediate frequency signal, and an RF output offset phase-locked loop responsive to the filtered intermediate frequency signal and the signal at the multiple of the intermediate frequency for producing an RF transmission signal. The harmonic rejection mixer reduces filtering requirements to facilitate a high level of circuit integration. The local oscillator may use a integer or fractional-N phase-locked loop.

Wireless communications transceiver: transmitter using a harmonic rejection mixer and an RF output offset phase-locked loop in a two-step up-conversion architecture and receiver using direct conversion architecture

In an exemplary application, an apparatus according to a disclosed embodiment receives a radio frequency signal and outputs an intermediate frequency signal. Rejection of image components in the intermediate frequency signal is obtained without the need to preprocess the radio frequency signal with an image reject filter. Such an apparatus may also exhibit an image rejection performance that is robust to frequency deviation of a local oscillator.

Quadrature generator with image reject mixer

A direct conversion receiver (200) is capable of recovering a filtered baseband signal (295) from a radio signal (201) modulated with a baseband signal (202). The direct conversion receiver (200) comprises a radio frequency mixer (205) for converting the radio signal (201) to the baseband signal (202), a lowpass amplifier (210) DC coupled to the radio frequency mixer (205), that amplifies the baseband signal (202) and substantially attenuates components of the baseband signal above a high corner frequency, and a DC offset compensation section (225) DC coupled to the lowpass amplifier (210), that provides a DC offset compensation and a controlled highpass filtering of the baseband signal. A low corner frequency of the DC offset compensation section is smoothly varied from a predetermined maximum value to a predetermined minimum value during a low frequency, low energy portion of the signaling protocol.

Radio having a fast adapting direct conversion receiver

A low power zero-IF selective call receiver has a local oscillator (106) that generates an injection signal for a first mixer (104) and a pair of quadrature phase related injection signals (122, 124) for a pair of second mixers (112, 114). The first mixer converts the received carrier signal (102) to an intermediate signal (108). A digital phase shifter/divider (116) coupled to the local oscillator (106) generates the pair of quadrature phase related injection signals (122, 124) at the frequency of the intermediate signal (108) which also equals the frequency of the local oscillator (106) divided by an integer greater then 1. The pair of second mixers (112, 114) coupled to the digital phase shifter/divider (116) converts the in and quadrature phase components (122, 124) of the intermediate signal (108) to respective in and quadrature phase baseband signals (126, 128).

Wide band zero if quadrature demodulator using a intermediate frequency

A volume control circuit for an audio transducer comprises a driver circuit driven by a first pulse rate signal to excite the audio transducer and render an audio signal at a desired volume and audio frequency corresponding to the first pulse rate signal, and a control circuit selectively activated to pulse modulate the excitation of the audio transducer during its pulsed excitation periods to alter the volume of the audio signal rendered by the audio transducer. In one embodiment, the control circuit includes a logical AND gate having as one input the first pulse rate signal and as another input a selected signal of either a second pulse rate signal or a signal representative of a logical one, the AND gate selectively activated to pulse rate modulate the first pulse rate signal with the second pulse rate signal which is preferably ultrasonic. In another embodiment, the AND gate may be coupled to a variable pulse rate signal to pulse rate modulate the first pulse rate signal to render the audio signal at a volume commensurate with the varied pulse rate. Various other alternate embodiments of the present invention are described all including the foregoing described volume control circuit.

Volume control circuit using pulse modulation

An encased electronic component comprises a casing (10) for protecting the component while exposing electrodes (or terminations) thereof for soldering. The casing includes an aperture for allowing air internal of the casing to exhaust upon heating during soldering so as to oppose the ingress of foreign material into the casing.

Encased electronic component

Growing community of inventors

Solana Beach, CA, United States of America

James Ian Jaffee