Maxeler Technologies Limited

James Huggett

Oliver Pell

Jacob Bower

Jacob Alexis Bower

Embodiments of the invention provide a method and apparatus for generating programmable logic for a hardware accelerator, the method comprising: generating a graph of nodes representing the programmable logic to be implemented in hardware; identifying nodes within the graph that affect external flow control of the programmable logic; retaining the identified nodes and removing or replacing all nodes which do not affect external flow control of the programmable logic in a modified graph; and simulating the modified graph or building a corresponding circuit of the retained nodes.

Method and apparatus for designing and generating a stream processor

There is provided a method of processing an iterative computation on a computing device comprising at least one processor. Embodiments of the method comprises performing, on a processor, an iterative calculation on data in a fixed point numerical format having a scaling factor, wherein the scaling factor is selectively variable for different steps of said calculation in order to prevent overflow and to minimize underflow. By providing such a method, the reliability, precision and flexibility of floating point operations can be achieved whilst using fixed point processing logic. The errors which fixed-point units are usually prone to generate if the range limits are exceeded can be mitigated, whilst still providing the advantage of a significantly reduced logic area to perform the calculations in fixed point.

Method and apparatus for performing numerical calculations

A method of generating a hardware design for a pipelined parallel stream processor. The method includes defining a processing operation designating processes to be implemented in hardware as part of said pipelined parallel stream processor and defining a graph representing said processing operation as a parallel structure in the time domain as a function of clock cycles. The method also includes defining the at least one data path and associated latencies of said graph as a set of algebraic linear inequalities, collectively solving the set of linear inequalities for the entire graph, optimizing the at least one data path in the graph using the solved linear inequalities to produce an optimized graph, and utilizing the optimized graph to define an optimized hardware design for implementation in hardware as the pipelined parallel stream processor.

Method of, and apparatus for, optimization of dataflow hardware

There is provided embodiment of methods of and apparatus for generating a hardware design for a pipelined parallel stream processor.

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London, United Kingdom

James Huggett