Xilinx, Inc.

James Hudner

Declan Carey

Brendan Farley

Darragh Walsh

Ivan Bogue

Marc Erett

Thomas Mallard

Mark Smyth

Apparatus and associated methods relate to a dynamic quantizer circuit including a tail voltage supply magnitude (VTAIL) distinct from a general supply voltage (Avcc/Avss), VTAIL providing power to a tail clock buffer to generate tail clock signals to tail devices. In an illustrative example, a compensation processor may control a regulator producing a determined VTAIL value in response to one or more parametric signals, for example, the Avcc voltage value, a circuit temperature and a transistor speed process (TSP). The TSP signal may be determined, for example, by process-dependent circuit devices. The compensation processor may be, for example, configured to lower VTAIL in response to detecting a worst-case RMS noise corner, or to raise VTAIL in response to detecting a worst-case clock-to-q corner. Various adjustable VTAILs may be configured to continuously optimize RMS noise, offset and speed performance with low power consumption in various quantizers over process, voltage and/or temperature.

Adaptable quantizers having dedicated supply voltage for tail device drivers

Various implementations are presented herein that improve the performance of dynamic quantizers over process, voltage and temperature ('PVT') and input common mode (Vcm) variations. This can be accomplished by separating and then varying the voltage supply to the reset devices connected to the input devices of the quantizer while leaving the supply to the other parts of the quantizer unchanged. The timing performance of the quantizer can be improved (reduced clock-to-q) by lowering the voltage supply to the reset devices. The input referred RMS noise and offset voltage of the circuit can be improved (reduced) by raising the voltage supply to the reset devices. Similarly, increases in Vcm due to process and voltage scaling can be mitigated by raising the voltage supply to the reset devices. Control systems are also provided herein to control the voltage supply to the reset devices to accomplish these and other objectives.

Dynamic quantizers having multiple reset levels

An apparatus relating generally to voltage conversion includes an amplifier coupled to receive an input voltage and a reference voltage. First and second converters are coupled to the amplifier to receive a bias voltage. The first converter includes a first transconductor coupled to receive the bias voltage to adjust a first tail current, and a first differential input. A first inverter of the first converter has a first feedback device coupled input-to-output to provide a first transimpedance amplifier load. The first inverter is coupled to the first transconductor. The second converter includes a second transconductor coupled to receive the bias voltage to adjust a second tail current, and a second differential input. A second inverter of the second converter has a second feedback device coupled input-to-output to provide a second transimpedance amplifier load. The second inverter is coupled to the second transconductor.

High-speed analog comparator

An analog-to-digital converter ('ADC'). The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.

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Charleville, Ireland

James Hudner