United Microelectronics Corp.

James Ho

Chen-Bin Lin

Cheng-Hui Chung

Yu-Ju Liu

Feng-Ming Liu

Chang Ping Lou

A method of manufacturing a mask ROM. A sacrificial silicon oxide layer is formed on the active region upon the substrate. Patterning the sacrificial silicon oxide layer in order to form a plurality of parallel openings, thereby exposing a portion of the active region. A polysilicon layer is formed on the openings and openings are formed thereon. An ion implantation process is performed on the polysilicon layer. Using a thermal flow process, the ions within the polysilicon layer are driven through the openings into the lower portion of the substrate, thereby forming an ion doping region. The polysilicon layer is etchbacked until the sacrificial silicon oxide layer is exposed. The sacrificial silicon oxide layer is removed.

Method of manufacturing a mask ROM bit line

An electrode plate assembly for installation to an etching console includes a cooling electrode plate, an aligning peg, a covering plate and a plurality of screws for coupling the electrode cooling plate and cover plate. The cooling electrode plate is formed of a metallic, disk-shaped electrode plate including an aligning peg securing hole, a plurality of first screw holes and a plurality of first vent holes. The aligning peg is located within the aligning peg securing hole and protrudes from the cooling electrode plate. The covering plate is a thin disk-shaped plate including an aligning peg receiving hole, a plurality of second screw holes and a plurality of second vent holes. Upon installation, the covering plate and the cooling electrode plate are coupled by a plurality of screws through the first and second screw holes, with the aligning peg received in the aligning peg receiving hole of the covering plate to assure proper alignment of the plates.

Alignment aid for an electrode plate assembly

A process for fabricating a mixed signal integrated circuit on a substrate, wherein the substrate is partially covered with a field oxide layer. An oxide layer is formed over a portion of the substrate, wherein the portion of the substrate is not covered with the field oxide layer. First impurities are implanted into the substrate, wherein the first impurities damage the oxide layer. A buffer layer is formed over the oxide layer. A polysilicon layer is formed over the buffer layer. Second impurities are implanted into the polysilicon layer, wherein the buffer layer prevents the oxide layer form being damaged by the second impurities. The polysilicon layer is etched to remove the polysilicon layer, wherein the buffer layer prevents the oxide layer and the substrate from being etched. The portion of buffer layer and the damaged oxide layer over the substrate are removed. The gate oxide layer is formed over the substrate.

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Taichung, Taiwan

James Ho