Unisys Corporation

James Henry Jeppesen, Iii

Bruce Ernest Whittaker

Edwin Jou

Kelly Sue St Clair-Hong

A computer network serviced by a maintenance subsystem holds a control processing module (CPM) holding a Data Path Array as interface to a main memory module and I/O Module. A maintenance controller in the CPM has a preloaded Flash Memory unit holding all the necessary operating addresses and data which can be rapidly transferred via a special wide parallel high speed data bus to a data path array unit for subsequent conveyance to a channel microcode block in a main memory module. The operating data include channel microcode data necessary for the I/O Module to communicate with different types of peripheral devices.

Fast write initialization method and system for loading channel adapter

A central processing module (CPM) uses a data path array interface connecting dual system busses to a main memory module and I/O module. A maintenance controller in the CPM manages a programmable array logic unit controller to read out microcode words in the main memory module to verify their accuracy by comparison with an original data base of microcode words in a flash memory which was earlier pre-loaded from a maintenance subsystem. A high speed auxiliary data bus controlled by the programmable array logic controller, provides a high speed transfer channel for moving the main memory words to the maintenance controller which can then institute a verification procedure for each memory word.

Processor path emulation system providing fast readout and verification

A computer network having a Control Processing Module (CPM) maintained by an external Maintenance Subsystem where the CPM has JTAG compatible digital units, but where the Cache Module is not JTAG compatible. Specialized transceivers having Boundary Scan Registers are activated to enable loading of address words in a Tag RAM while concomitantly placing correct initial parity data in a Parity RAM without need to continue communication with the external Maintenance Subsystem. The Boundary Scan Registers in said transceivers are set up to perform as up-counters to sequence through all address locations in the Tag RAM while a Control PAL calculates and places the associated parity values in each corresponding address location in the Parity RAM.

High speed initialization system for RAM devices using JTAG loop for

A network comprising a central processing module and maintenance subsystem which provides a system for rapid loading of instruction words in a microcode RAM whereby microcode instruction words from the maintenance subsystem are preliminarily loaded into a flash memory in the central processing module. A maintenance controller transfers the microcode instruction words from the flash memory over a transfer bus to a data path array which connects to a processor-instruction memory bus for enabling microcode addresses and data words to be rapidly transferred into a microcode RAM instruction memory. A programmable controller activated by the maintenance controller in the central processing module then regulates the transfer of data to the microcode RAM by providing incrementation of the addresses of the instruction words on an automatic basis and thus relieving the processor of this function. Due to the pre-loading of the microcode instruction words into flash memory of the central processing module, there is provided a rapid loading of the microcode RAM during initialization routines without the need to burden the processor or the maintenance subsystem.

Fast write initialization system for microcode RAM via data path array

A system and method for using standard JTAG protocol for testing protocol compliant and non-protocol compliant digital devices without altering the JTAG protocol or the non-compliant device. A specialized Test Access Port Controller controls and monitors the states applied to the non-compliant device in order to eliminate the PAUSE state in the non-compliant device and to limit the Run-Test/Idle state to one clock period.

JTAG interface system for communicating with compliant and non-compliant

A digital system which normally initializes and tests non-JTAG logic units is adapted to test JTAG protocol compatible logic units. A JTAG translator unit provides an instruction control register and a Data Register. The Control Register has control bits for selecting Test-Mode-Select and Test Clock signals for the JTAG compatible units and Shift/Hold signals for the non-JTAG compatible logic units. The Data Register supplies diagnostic test bits to registers in both the JTAG and non-JTAG logic units. Additionally, the Control Register can initiate automatic incrementation of addresses to a control state RAM for rapid loading of microcode.

System for adapting maintenance operations to JTAG and non-JTAG modules

A system whereby a microcode RAM in a central processing module can have each microcode word rapidly accessed and transferred to a maintenance controller to compare each accessed microcode word with a corresponding microcode word in a set of microcode words which were pre-loaded in a flash memory.

System for fast read and verification of microcode RAM

A system for equal utilization of blocks of flash memory whereby a processor using algorithmic software functions to sort the usage-value of each block of flash memory so that the system will select the least-used memory block for the next cycle of memory usage. The described system provides direct and immediate access of flash memory to the microprocessor without any intermediate modules or vias which would delay that access. Further, a minimal amount of overhead header information is only required for each flash memory block thus allowing greater areas of memory usage for instructional code data.

Flash memory wear leveling system providing immediate direct access to

Control signals are provided for data transfer timing compatibility between two systems or two modules which are not synchronous with each other. Specialized circuitry is provided to ensure timing compatibility in that control signals, transmitted from one system to the other, are handled by interface circuitry which directly transmits the front-end transition and delays the back-end transition so it can be synchronized to the receiving systems clock.

Half synchronizer circuit interface system

In a system of multiple digital modules which is operated synchronously via common clock means, there is provided circuitry for halting each module at the same simultaneously clock-moment after sensing of a selected condition in any one of the digital modules.

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Lake Forest, CA, United States of America

James Henry Jeppesen, Iii