Compaq Computer Corporation, Inc.

Hewlett Packard Enterprise Development LP

James H Singer

William C Galloway

Jeffrey S Autor

John M Hemphill

Dennis J Alexander

Alexander C Ekrot

John Norton

Joseph R Allen

Joseph P Miller

Bradley E Mayes

Examples disclosed herein provide a compute server system comprising a plurality of nodes. In one example, each node generally includes a replaceable power source externally accessible to the node, and a guide for housing the replaceable power source. The guide generally includes conductive elements to make contact with conductive elements of the replaceable power source, and an elastic member to eject the replaceable power source from the node.

Externally accessible replaceable power source

A digital system that includes a main printed circuit board that has a first conductive portion formed thereon is provided. A microprocessor module is coupled to and extends orthogonally from the first conductive portion of the main circuit board. A voltage regulator printed circuit board is coupled to and extends orthogonally from the first conductive portion of the main circuit board adjacent the microprocessor module. The voltage regulator printed circuit board supplies a regulated voltage to the microprocessor module over the first conductive portion.

Voltage regulator module

A technique for reducing skew between clock signals in a digital system requiring multiple clock signals. The system preferably is implemented on a printed circuit board. An oscillator circuit provides a periodic signal to a clock buffer which generates multiple periodic clock signals. The clock signals are provided to various destination points on the printed circuit board. The rising and falling edges of each clock signal generated by the clock buffer do not occur precisely at the same time as the rising and falling edges of the other clock signals. This misalignment of clock edges, or skew, is detrimental to system performance, but is reduced substantially by connecting all of the clock buffer's output clock signals together at a single physical point or node. Accordingly, the printed circuit board traces carrying each of the clock signals are routed to a single point node. A single point node is used to reduce skew caused by the clock buffer. Single point nodes also may be used at various locations on the printed circuit board to reduce skew caused by differences in the lengths of the traces carrying the clock signals.

Clock skew reduction using spider clock trace routing

A primary server/standby server network configuration according to the invention includes a primary server executing network operating system software and a standby server monitoring for the proper operation of the primary server, where both the primary server and the standby server are connected to a storage system. If the primary server fails, the standby server instructs the storage system to switch its hardware connections to the standby server, allowing the standby server to boot the operating system. This instruction is done via in-band signaling. Further, multiple primary servers can be backed up by a single standby server.

Multi-server fault tolerance using in-band signalling

An improved printed circuit board layout is provided in which a transistor or a resistor (preferably a zero ohm resistor) can be installed. If a transistor is installed, this allows for selectively passing a signal; if a resistor is installed, the line is directly coupled. The resistor and transistor are surface mount devices, and the two pads for the resistor are overlapped with two of the pads for the source and the drain of the transistor. A separate pad is provided for the gate of the transistor. In this way, alternatively either a resistor or a transistor can be installed, but the trace links, stubs, and resulting undesirable effects are minimized through the overlapping pads.

Growing community of inventors

Houston, TX, United States of America

James H Singer