Motorola Corporation

Semiconductor Components Industries, LLC

James H Knapp

Francis J Carney, Jr

Keith E Nelson

Laura J Norton

Stephen St Germain

Albert J Laninga

Francis J Carney

Joseph E Sauvageau

James Price Letterman, Jr

Cynthia M Melton

Joseph K Fauty

George F Carney

George Amos Carson

Harold Anderson

Harry Fuerhaupter

Phillip C Celaya

Donald H Klosterman

Frank Tim Jones

Michael John Seddon

Jay A Yoder

George W Hawkins

Brian A Webb

John Baird

Barbara M Foley

Yenting Wen

Prosanto K Mukerji

William F Burghout

Harry J Geyer

Ronald E Thomas

Dwight L Daniels

Cliff J Scribner

Guan Keng Quah

Timothy Lee Johnson

Rajesh Srinivasan

Cang Ngo

Michael L Majercak

Setsuko J Cole

Colin B Bosch

Edward M Majors

Michael C Majercak

Les Ticey

Kevin J Foley

Beng Lian Lim

Kok Yang Lau

A semiconductor device () is made by mounting the bottom surfaces () of a semiconductor die () and a lead () on a tape () and over a hole () in the tape. A vacuum is drawn through the hole to secure the die in place when the lead's top surface () is wirebonded to a top surface () of the semiconductor die. A molding material () is formed to encapsulate the top surface of the semiconductor die and to expose its bottom surface.

Method of marking a low profile packaged semiconductor device

A semiconductor device () includes a semiconductor die () and an inductor () formed with a bonding wire () attached to a top surface () of the semiconductor die. The bonding wire is extended laterally a distance (L, L) greater than its height (H, H) to define an insulating core (). In one embodiment, the inductor is extended beyond an edge () of the semiconductor die to reduce loading.

Semiconductor device with wire bond inductor and method

A method of forming a leadframe and a semiconductor package using the leadframe facilitates selectively forming leads for the package. The leadframe is formed with a first portion of the leads extending from a panel of the leadframe into a molding cavity section of the leadframe. After encapsultaion, a portion of the leadframe panel is used to form a second portion of the leads that is external to the package body.

Method of forming a semiconductor package and leadframe therefor

A method for forming a direct chip attach (DCA) device ( ) includes attaching a chip ( ) to a lead frame ( ). Conductive studs ( ) are attached to bonding pads ( ) on the chip ( ) and a flag ( ) on lead frame ( ). The chip ( ) and flag ( ) are enclosed with an encapsulating layer ( ), and openings ( ) are formed in an upper surface ( ) to expose conductive studs ( ). In one embodiment, a masking layer ( ) is applied to the lead frame ( ), and the structure is then placed in an electroless plating apparatus ( ). While in the plating apparatus ( ), an injection device ( ) injects plating solution ( ) towards the upper surface ( ) and openings ( ) to enhance the formation of barrier layers ( ) on the conductive studs ( ). Solder bumps ( ) are then attached to barrier layers ( ) through the openings ( ).

Direct chip attach structure and method

A semiconductor device ( ) has a first leadframe ( ) with a first semiconductor die ( ) electrically coupled to one of its leads. A second semiconductor die ( ) is mounted to a second leadframe ( ) that has a first lead ( ) electrically coupled to the second semiconductor die and a second lead ( ) mounted to the lead of the first leadframe.

Structure and method of forming a multiple leadframe semiconductor device

An integrated circuit ( ) includes a semiconductor die ( ) and a semiconductor package ( ) that has a leadframe ( ) for mounting the semiconductor die. The leadframe includes a first laminate ( ) whose bottom surface ( ) is patterned with leads ( ) of the integrated circuit. A second laminate ( ) has a bottom surface ( ) attached to a top surface ( ) of the first laminate to electrically coupling the leads to the semiconductor die.

Integrated circuit and laminated leadframe package

A method of making a semiconductor device ( ) by attaching a top surface of a first laminate ( ) to a bottom surface of a second laminate ( ) to form a leadframe ( ) and mounting a semiconductor die ( ) to the leadframe to form the semiconductor device. The first semiconductor die is encapsulated with a molding compound ( ) and material is removed from the first laminate to form a mold lock ( ) with the molding compound.

Semiconductor device and laminated leadframe package

A semiconductor component includes a semiconductor chip (,) having first and second surfaces opposite each other, a semiconductor device (,) in the semiconductor chip (,), and a flexible substrate (,) packaging the semiconductor chip (,).

Flexible substrate for packaging a semiconductor component

An optical coupler (60) includes of an optical connector (10) coupled to an optoelectric board (64). An optical fiber (50) is inserted into the optical connector (10). The optical fiber (50) is bent to an angle of approximately 90.degree. inside the optical connector (10). A tip (55) of the optical fiber (50) is substantially perpendicular to the optoelectric board (64) and aligned to an optical region of an optoelectric device (62) on the optoelectric board (64). A portion of the optical fiber (50) outside the optical connector (10) is substantially parallel to the optoelectric board (64). A fiber retainer (30) secures the optical fiber (50) to the optical connector (10).

Optical coupler and method for coupling an optical fiber to an

A microelectronic package (10) is formed and includes an integrated circuit die (12) attached to a substrate (14) by a plurality of solder bump interconnections (16) to form a preassembly (18). The integrated circuit die (12) has an active face (20) that faces the substrate (14) and is spaced apart therefrom by a gap (22). The integrated circuit die (12) also includes a back face (24) opposite the active face (20). The substrate (14) includes a die attach region (26) and a surrounding region (28) about the integrated circuit die (12). The solder bump interconnections (16) extend across the gap (22) and connect the integrated circuit die (12) and the substrate (14). A mold (30) is disposed about the preassembly (18) such that the mold (30) cooperates with the substrate (14) to define a mold cavity (32) that encloses the integrated circuit die (12). The mold (30) has a molding surface (34) that includes the surrounding region (28) and a mold surface (34) that faces the back face (24) and is spaced apart therefrom. A polymeric precursor (36) is dispensed into the mold cavity (32) and is formed against the molding surface (34) and the back face (24). The polymeric precursor (36) is then cured to form a polymeric encapsulant (38) that encapsulates the integrated circuit die (12).

Microelectronic package including a polymer encapsulated die

An electronic component includes a substrate (301, 801), a leadframe (101, 601, 710) coupled to a first surface of the substrate (301, 801) and extending beyond the first surface and towards a second surface of the substrate (301, 801), and an electrically conductive layer coupled to the second surface and coplanar with a contact portion of the leadframe (101, 601, 710) where the leadframe (101, 601, 710) and the electrically conductive layer form a package around the substrate (301, 801).

Semiconductor package consisting of multiple conductive layers

A semiconductor device (10) coupled to ball grid array substrate (11) and encapsulated by an optically transmissive material (29, 31). The ball grid array substrate (11) has conductive interconnects (14) and a semiconductor receiving area (17) on a top surface and solder pads (13) on a bottom surface. An optoelectronic component (24) is mounted on the semiconductor receiving area (17) and encapsulated with the optically transmissive material (29, 31). Solder balls (18) are formed on the solder pads (13).

Ball grid device with optically transmissive coating

An optoelectronic connector (10) coupled to a fiber ferrule (38) containing an optical fiber (39) and a method for coupling the optoelectronic connector (10) to the fiber ferrule (38). The optoelectronic connector (10) has a base (11) and walls (13, 14, 17, and 18) that form a cavity (19). A semiconductor receiving area (26) extends into a first portion of the base (11) and an interconnect recess (27) extends into a second portion of the base (11). Alignment pins (31) extend from the second portion of the base (11). The optoelectronic connector (10) may be a unitary structure. The fiber ferrule (38) is inserted into the cavity (19) to form an optoelectronic device (30).

Optoelectronic device and method of assembly

A method of manufacturing a semiconductor component includes forming a vertical side seal for a runner in a first mold plate by mating a protrusion of the first mold plate with a protrusion of a second mold plate. As an encapsulating material is forced through the runner, the vertical side seal prevents an encapsulating material from leaking out of the edge of the runner.

Method of manufacturing a semiconductor component

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Chandler, AZ, United States of America

James H Knapp