Motorola Corporation

Freescale Semiconductor,inc.

James H Kleffner

Addi B Mistry

Daryl R Wilde

David Patten

Vijay Sarihan

George F Carney

Joseph M Haas

John Gehman

Brian H Christensen

John Rohde

Dennis O Kiffe

A stacked die system () has a first die () having a first surface with active circuitry, a second die () having a first surface with active circuitry, and a conductive shield () interposed between the first surface of the first die and the first surface of the second die. In one embodiment, the distance between the first surfaces of the first and second die is less than one millimeter. The stacked die system may also include a package substrate () where the active circuitry of the first and second die are electrically connected to the package substrate. The electrical connections may be formed using wire bonds (). Alternatively, the first die may be connected to the package substrate in a flip chip configuration. In one embodiment, the active circuitry of the first die generates RF signals where the shield helps protect the RF signals from interference caused by the active circuitry of the second die.

Digital and RF system and method therefor

A semiconductor package assembly has an intervening package ( ) that may be connected to a first package ( ) from a first substrate ( ) on a first side of the package ( ) and to a second package ( ) from a second substrate ( ) on a second, opposing side of the package ( ). Electrical contact to a semiconductor die ( ) is made from the first side by wire bonding to wire bond posts ( ) and by balls ( ) from the second side. Electrical contact from one side of the intervening package ( ) to the other may be made by bypassing the die. Electrical contact on either side of the intervening package may be made both within and outside the footprint of the semiconductor die ( ).

Semiconductor package with multiple sides having package contacts

A semiconductor device (10) includes a bump structure that reduces stress and thus reduces passivation cracking and silicon cratering that can be a failure mode in semiconductor manufacturing. The stress is reduced by forming a polyimide layer (16) over a passivation layer (14). The polyimide layer (16) is extended beyond an edge of the passivation layer (14) over the metal pad (12). A solder bump (22) is composed of a eutectic material and is formed on the metal pad (12) and on the polyimide layer (16). The polyimide layer (16) prevents the solder bump (22) from contacting the passivation layer (14). This is useful for electroless or electroplating technology and may also be useful in other types of bump forming technology such as C4 and E3.

Method and apparatus for stress relief in solder bump formation on a

A bumped semiconductor device including bond pad (12) formed on a semiconductor die (10), and a passivation layer (14) overlying the semiconductor die and a portion of the bond pad (12). A solder bump (22) is formed so as to overlie the bond pad (12), and a stress isolation trench (15) is formed in the passivation layer (14), so as to surround the solder bump (22).

Bumped semiconductor device having a trench for stress relief

Growing community of inventors

Leander, TX, United States of America

James H Kleffner