Lara Technology, Inc.

James G Washburn

Ajit K Medhekar

Jayan R Ramankutty

A modified binary content addressable memory (CAM) (,) having a fast variable prefix matching capability is disclosed. The modified CAM (,) includes modified CAM cells (,(,) to,(n,m)), each of which includes a store/compare circuit (,(,) to,(n,m)) for storing a data value and comparing the data value to a comparand value. In addition, each modified CAM cell (,(,) to,(n,m)) further includes a multiplexer (MUX) circuit (,(,) to,(n,m)). Each MUX circuit (,(,) to,(n,m)) receives a non-shifted comparand value from a modified CAM cell of a previous row and same column, and a shifted comparand value from a modified CAM cell of the previous row and an adjacent column. The MUX circuits (,(,) to,(n,m)) enable a comparand value to be shifted as it is applied to consecutive data values.

Enhanced binary content addressable memory for longest prefix address matching

A ternary content addressable memory (CAM) (800) having a massive, parallel shift capability is disclosed. The CAM (800) includes an array of CAM cells (802(1,1) to 802(1,4)), each of which includes a data value register (804(1,1) to 804(1,4)) and a mask value register (806(1,1) to 806(1,4)). To enable parallel shifting between a CAM cell in one row with a corresponding CAM cell in a higher row, each data value register (804(1,1) 804(1,4)) and mask value register (806(1,1) to 806(1,4)) includes an upper data input (UD) coupled the output of a CAM cell in the higher row. To enable parallel shifting between a CAM cell in one row with a corresponding CAM cell in a lower row, each data value register (804(1,1) 804(1,4)) and mask value register (806(1,1) to 806(1,4)) includes a lower data input (LD) coupled the output of a CAM cell in the lower row.

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Palo Alto, CA, United States of America

James G Washburn