Motorola Corporation

James G Viot

Oded Yishay

James L Broseghini

Eytan Hartung

Avinash C Palaniswamy

Donald H Lenhert

A method, pager, cellular telephone, and apparatus (24) that includes a central processing unit (10) for providing at least one addressing signal, a change of flow signal, and a memory request signal; and at least one memory unit (12) having a memory cell array (14). When the memory request signal is asserted, the at least one memory unit (12) sequentially selects a plurality of memory cells in the memory cell array (14) for accessing information therein, and when the change of flow signal is asserted, the sequential selection of the plurality of memory cells by the at least one memory unit (12) is inhibited and a predetermined memory cell is selected, determined by the at least one addressing signal, for accessing information in the predetermined memory cell.

Method, apparatus, pager, and cellular telephone for accessing

A pipelined data processor (10) has a control unit (14') that detects an illegal instruction as well as legal instruction opcodes. An opcode decoder (28) decodes instructions. In response to decoding an illegal instruction, opcode decoder (28) provides no output signal. In response to decoding a legal instruction, opcode decoder (28) provides one of a plurality of output signals. A ROM (27) provides a first output in response to receiving no output from the decoder (28), and provides one of a plurality of second outputs in response to receiving one of a plurality of output signals from decoder (28). The first output of the ROM (27) is a first microword of a routine for processing the illegal instruction. Each of the second outputs of the ROM (27) is a first microword of a routine for processing the legal instruction received from the decoder (28).

Pipelined data processor that detects an illegal instruction by

A method and apparatus for generating pseudo-random numbers or for performing data compression in a data processor (12). In one form, the present invention generates pseudo-random numbers which are used to provide scan input data bits during built-in-self-test (BIST) scan testing. The present invention then performs data compression on the scan output data received back from the circuits under test (73-75). In one embodiment, the BIST scan testing of data processor (12) is performed in a special 'background self-test mode'. Central processing unit (CPU) 20 is used to generate the pseudo-random numbers and to perform the data compression. CPU 20 also functions as a standard CPU when in a normal operating mode.

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Austin, TX, United States of America

James G Viot