Altera Corporation

Efinix, Inc.

Other

James G Schleicher

Bruce B Pedersen

Andy Louie Lee

Sergey Yuryevich Shumarayev

David Lewis

Rakesh H Patel

Wei-Jen Huang

Tony K Ngai

Victor Maruri

Gregg William Baeckler

Sinan Kaptanoglu

Richard Yuan

Mike Hutton

Henry Kim

Rahul Saini

Michael David Hutton

David Wolk Mendel

Jim Park

Andrew Leaver

Peter J Kazarian

Vaughn Betz

James Park

Richard G Cliff

Christopher F Lane

Srinivas T Reddy

Cameron R McClintock

David Edward Jefferson

Manuel M Mejia

Bruce B Pederson

Stephen D Brown

Ninh D Ngo

Babette Van Antwerpen

Terry Borer

Timothy J Southgate

Kevin Chan

Ian Chesal

Boris Ratchev

Yaska Sankar

Michael J Ferrazano

Martin Langhammer

Jinyong Yuan

David Karchmer

Marcel A LeBlanc

Scott D Redman

Jeffrey Chen

A system having design tools and methods for using the same in designing an integrated circuit (IC) are described. In one embodiment, an IC design system, the system comprises one or more processors; and a non-transitory computer readable medium connected to the one or more processors, wherein the non-transitory computer readable medium is configured to store: a first design tool module configured to determine one or more design specifications for a core of an integrated circuit (IC), the IC comprising a plurality of transistors and other components, and a plurality of interconnects between the transistors and the other components, wherein the plurality of transistors and the other components and the plurality of interconnects are formed on a single die, and a second design tool module configured to determine one or more design specifications for a periphery of the IC, the second tool to function independently of the first tool and operable to design constraints for interface placement and configuration of an interface between the core and the periphery of IC.

Peripheral tool

A system having design tools and methods using the same design tools in designing an integrated circuit (IC) are described. In one embodiment, an IC design system comprises, the system comprises one or more processors; and a non-transitory computer readable medium connected to the one or more processors, wherein the non-transitory computer readable medium is configured to store: of a first design tool module configured to determine one or more design specifications for a core of an integrated circuit (IC), the IC comprising a plurality of transistors and other components, and a plurality of interconnects between the plurality of transistors and the other components, wherein the plurality of transistors and the other components and the plurality of interconnects are formed on a single die, and a second design tool configured to determine one or more design specifications for a periphery of the IC, the second design tool module to function independently of the first design tool module and operable to design constraints for interface placement and configuration of an interface between the core and the periphery of the IC.

Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.

Omnibus logic element

Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Omnibus logic element for packing or fracturing

A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

Interconnection and input/output resources for programmable logic integrated circuit devices

Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.

Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage

Logic circuits that support the addition of three binary numbers using hardwired adders are described. In one embodiment, this is accomplished by using a 3:2 compressor (i.e., a Carry Save Adder method), using hardwired adders to add the sums and carrys produced by the 3:2 compression, and sharing carrys data calculated in one logic element ('LE') with the following LE. In such an embodiment, with the exception of the first and last LEs in a logic array block ('LAB'), each LE in effect lends one look-up table (&#x201c;LUT&#x201d;) to the LE below (i.e., the following LE) and borrows one LUT from the LE above (i.e., the previous LE). The LUT being lent or borrowed is one that implements the carry function in the 3:2 compressor model. In another aspect, an embodiment of the present invention provides LEs that include selectors to select signals corresponding to the addition of three binary numbers mode.

Logic cell supporting addition of three binary words

An interface for a programmable logic device having a non-volatile memory where a portion of the non-volatile memory is user accessible is provided. A megafunction provides the electronic circuit designer with interface protocol options for the user accessible portion of the non-volatile memory block. The circuitry associated with the user selected interface is then programmed into the programmable logic device.

User non-volatile memory interface megafunction

Growing community of inventors

Sunnyvale, CA, United States of America

James G Schleicher