Motorola Corporation

Freescale Semiconductor,inc.

James G Mittel

Walter L Davis

Raymond Louis Barrett

John J Parkes, Jr

Michael J DeLuca

Richard Alexander Erhart

John M McKee

Edgar Herbert Callaway, Jr

Barry W Herold

Scott R Humphreys

Kazimierz Siwiak

Mahibur Rahman

David F Willard

Clinton C Powell, Ii

Lorenzo A Ponce De Leon

Philip P Macnak

Christopher T Thomas

Burkhard Dick

John Wayne Simmons

Raymond L Barrett, Jr

Gerald E Brinkley

Walter J Grandfield

Mark L Oliboni

Vance H Peterson

Manbir Nag

Robert K Schweickert

James J Riches

Knud Holtvoeth

Wilfried E Knop

Kenneth D Fisch

Winfield J Brown, Jr

Philip A Kitching

Philip L Johnson

Darrell Curtis Weber

Sergio Fernandez

A power management system has a primary power source () and a secondary power source () generated from the primary power source () with a power output selector () coupled to each for selecting power for a regulated power output (). First, during initialization and at any other time during operation, when the primary power source () exceeds the secondary power source (), the primary power source () is used as a power supply for the regulated power output (). Second, at any time after initialization that the primary power source () exceeds the regulated power output (), the primary power source () is used as the power supply for the regulated power output (). Third, at any time after initialization that the secondary power source () exceeds the primary power source () and the primary power source () is less than the regulated power output (), the secondary power source () is used as the power supply for the regulated power output ().

Dual mode power management system

A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.

Clock jitter minimization in a continuous time sigma delta analog-to-digital converter

A sigma-delta converter operates over a predetermined bandwidth and includes a feedback loop comprising a forward path and a feedback path. The forward path includes, in series, a summer, a filter, and a comparator. The comparator produces an output signal that is fed back to a negative input of the summer via the feedback path. The sigma-delta converter also includes at least one instability generator positioned in the forward path and/or the feedback path. The instability generator generates one or more out-of-band instabilities in the feedback loop to substantially improve the in-band signal-to-noise performance of the converter for input signal amplitudes near a low end of the converter's dynamic range. The converter may be employed as an A/D converter, a D/D converter, or a D/A converter in a receiver and/or a transmitter of a wireless communication device.

Self-dithering sigma-delta converter and communication device incorporating same

A digital DC offset correction circuit ( ) provides DC offset correction within a receiver ( ) using an area-optimum, rapid acquisition cellular multi-protocol digital dc offset correction scheme. The digital DC offset correction circuit ( ) includes an integrator ( ), a low pass filter ( ), a decimator ( ), a digital to analog converter codeword clamp ( ), and a digital to analog converter ( ).

Area-optimum rapid acquisition cellular multi-protocol digital DC offset correction scheme

A DC offset correction circuit ( ) provides DC offset correction within a receiver ( ) for receiving and processing a radio frequency signal ( ) within a radio communication system ( ). The DC offset correction circuit ( ) includes a feedback loop ( ) for shifting a digital signal ( ) by a programmable amount; and a coarse DC offset correction path ( ) coupled to the feedback loop ( ) for performing coarse DC offset correction.

DC offset correction scheme for wireless receivers

A digital tuning circuit ( ) for a filter ( ) has a filter input and a filter output and employs a switchable element array ( ). The filter includes a tuning signal generator ( ) that generates a tuning signal ( ) that is delivered to the filter input and a clock circuit ( ) that generates a periodic stream of pulses. The digital tuning circuit includes a delay circuit ( ), a phase comparator ( ) and an integrating up-down counter ( ). The delay circuit ( ) is responsive to the tuning signal generator ( ) and delays the tuning signal ( ) by a predetermined amount corresponding to the nominal delay through the filter ( ). The integrating up-down counter ( ) counts pulses in a first direction when the phase comparator ( ) generates the first value and counts pulses in a second direction, opposite from the first direction, when the phase comparator ( ) generates the second value. The integrating up-down counter ( ) generates a binary word having a value corresponding to a number of counts that the integrating up-down counter ( ) performs and is coupled to the switchable element array ( ) so that a number of switchable elements is electrically coupled to the filter ( ). The number of switchable elements corresponds to the value of the binary word.

Digital filter tune loop

A selective call receiver (,) includes a radio receiver (,) and a processor (,). The radio receiver includes an antenna (,), a combination circuit (,), a bandpass filter (,), mixers (,), analog-to-digital converters (,), digital mixers (,), a second combination circuit (,), and a digital-to-analog converter (,). The combination circuit receives an analog signal from the antenna and combines the same with an analog feedback signal generated by the digital-to-analog converter. The bandpass filter filters the output of the combination circuit and supplies its output to the mixers which down-convert the signal to baseband signals. These signals are modified by the analog-to-digital converters to digital signals which are up-converted by the digital mixers. The outputs of the digital mixers are combined by the second combination circuit to a digital output that is modified by the digital-to-analog converter to the analog feedback signal.

Selective call receiver having an apparatus for modifying an analog signal to a digital signal and method therefor

A sigma delta analog-to-digital converter (100) comprising a second or third order integrator block (105) featuring a feed-forward connection path between the input of the integrator block and an input of at least one of the plurality of integrators (130 or 150). A comparator (180) coupled to the output of the integrator block (105) generates as output a digital value representing a difference between the integrator output signal with respect to a threshold, or in a differential mode implementation, between component signals of a differential signal output by the integrator block (105). A digital sampling element (190) coupled to the output of the comparator (180) samples the output of the comparator (180) in response to a sampling clock signal at a predetermined sampling frequency to generate as output digital signal comprising samples of the digital values output by the comparator (180).

Sigma delta data converter with feed-forward path to stabilize

A communication receiver (600) utilizes a band-pass sigma-delta converter (100) for receiving a radio signal. The band-pass sigma-delta converter (100) includes a comparator (106) coupled to an adder-filter (101) for making a comparison between a predetermined reference level (110) and an intermediate signal (125), and for generating a comparison result signal (114) responsive to the comparison. A storage element (108) is used for storing the comparison result signal (114) for a predetermined delay period, thereby producing a clocked output signal (118). The adder-filter (101) is coupled to an analog signal (103) and to the clocked output signal (118) for subtracting the clocked output signal (118) from the analog signal (103) to produce a difference signal (120) that is filtered by a commutating filter (400) for generating the intermediate signal (125) responsive to the difference signal (120).

Band-pass sigma-delta converter and commutating filter therefor

A mode tracking transducer driver (100) for a non-linear electromagnetic transducer (102) includes a voltage controlled oscillator (104) coupled within a phase lock loop to a transducer driver (106) and a mode detector (112, 108). The voltage controlled oscillator (104) generates a variable frequency output signal, and is responsive to a frequency control signal for controlling the frequency of the output signal. The transducer driver (106) generates a transducer drive signal (502) which is coupled to the non-linear electromagnetic transducer (102) to generate a tactile alert. The mode detector (112, 108) detects a mode change between at least the first operating mode and the second operating mode of the non-linear electromagnetic transducer (102), and in response thereto generates the frequency control signal (118) which establishes a quasi-resonant frequency (204) at which the tactile energy delivered by the non-linear electromagnetic transducer (102) is maximized.

Mode tracking transducer driver for a non-linear transducer

A frequency synthesizer (100) is utilized for producing an output signal (124) which is phase locked to a reference signal (110) operating at a reference frequency. The frequency synthesizer (100) comprises a main phase lock loop (PLL) (102), and a tracker PLL (128). The main PLL (102) includes a phase detector (112), two frequency dividers (108, 126), a loop filter (116), a notch filter (118), and a controlled oscillator (122). The tracker PLL (128) phase locks to the reference signal (110), and biases the notch filter (118) in order to maintain an accurate lock on the notch frequency which is proportional to the reference frequency. All circuits are integrated in the same monolithic device in order to track parametric tolerances such as transconductances of the operational transconductance devices included in the tracker PLL (128) and the notch filter (118).

Low-noise frequency synthesizer

In-phase (I) and quadrature-phase (Q) baseband signals (312, 314) are derived from a digitized signal (318) having a sampling rate. The digitized signal is band pass filtered (604) to produce a band passed signal (320), and the band passed signal is delayed (606) to produce a delayed band passed signal (322). The band passed signal and the delayed band passed signal are decimated (608) by a predetermined amount to produce, respectively, a decimated signal (328) and a decimated delayed signal (330). The decimated signal and the decimated delayed signal are low pass filtered (610) to produce, respectively, the I and Q baseband signals.

Apparatus for deriving in-phase and quadrature-phase baseband signals

A receiver (100) for receiving an input signal and generating an output signal therefrom has a switchable gain circuit (104) with a stepwise variable gain control (118), a local oscillator (106) and an automatic gain control (AGC) detector (114) with a response for detecting a level of the output signal and generating an AGC signal indicative of the level of the output signal and a state machine (116) being responsive to the AGC signal generating a control signal at the stepwise variable gain control to increase or decrease a gain of the switchable gain circuit in discrete stepwise steps.

Selective call receivers with stepwise variable gain control

A communication system (100) for selectively providing repeat messages includes a message transmission device (105) for normally transmitting messages a single time, for receiving repeat requests indicating that a previously transmitted message should be transmitted again, and for automatically transmitting future messages more than once in response to determining that a number of repeat requests exceeds a transmission threshold. A radio communication device (110) is included in the communication system (100) for receiving the messages and for generating a repeat request in response to determining that the previously transmitted message has not been correctly received.

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Boynton Beach, FL, United States of America

James G Mittel