Oracle America, Inc.

Oracle International Corporation

James G Mitchell

John E Cunningham

Ashok V Krishnamoorthy

Eugene Michael Chow

Ivan Shubin

Robert J Drost

Brian Walter O'Krafka

David C Douglas

Craig A Stephen

A multi-level interposer plate and a multi-chip module (MCM) that includes the multi-level interposer plate are described. First surfaces and second surfaces in different regions of the multi-level interposer plate have associated, different thicknesses. Moreover, first micro-spring connectors and second micro-spring connectors are respectively disposed on the first surfaces and the second surfaces. In the MCM, a given one of the first surfaces of the multi-level interposer plate faces a bridge chip in a first layer in an array of chips in the MCM so that first connectors, disposed on the bridge chip, mechanically and electrically couple to the first micro-spring connectors. Similarly, a given one of the second surfaces of the multi-level interposer plate faces an island chip in a second layer in the array of chips so that second connectors, disposed on the island chip, mechanically and electrically couple to the second micro-spring connectors.

Method for fabricating multi-chip module with multi-level interposer

A chip package includes a substrate having a positive feature, which is defined on a surface of the substrate and which protrudes above a region on the surface proximate to the positive feature. Furthermore, the chip package includes a mechanical reinforcement mechanism defined on the substrate proximate to the positive feature that increases a lateral shear strength of the positive feature relative to the substrate. In this way, the chip package may facilitate increased reliability of a multi-chip module (MCM) that includes the chip package.

Chip package with reinforced positive alignment features

A chip package is described. This chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. For example, the ramp component may be electrically coupled to the semiconductor dies using: microsprings, an anisotropic film, and/or solder. Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.

High-bandwidth ramp-stack chip package

Multi-chip module with multi-level interposer

Embodiments of a method for assembling a multi-chip module (MCM) are described. During this method, a fluid that includes coupling elements is applied to a surface of a base plate in the MCM. Then, at least some of the coupling elements are positioned into negative features on the surface of the base plate using fluidic assembly. Note that a given coupling element selects a given negative feature using chemical-based selection and/or geometry-based selection. Next, the fluid and excess coupling elements (which reside in regions outside of the negative features on the surface) are removed.

Self-assembly of micro-structures

Embodiments of a multi-chip module (MCM) are described. This MCM includes a first semiconductor die and a second semiconductor die, where a given semiconductor die, which can be the first semiconductor die or the second semiconductor die, includes proximity connectors proximate to a surface of the given semiconductor die. Moreover, the given semiconductor die is configured to communicate signals with the other semiconductor die via proximity communication through one or more of the proximity connectors. Furthermore, the MCM includes an alignment plate and a top plate coupled to the alignment plate. This alignment plate includes a first negative feature configured to accommodate the first semiconductor die and a second negative feature configured to accommodate the second semiconductor die, and the top plate includes a positive feature. Note that the positive feature is coupled to the first semiconductor die, and the positive feature facilitates mechanical positioning of the first semiconductor die.

Integrated-circuit package for proximity communication

Embodiments of a system are described. This system includes an array of chip modules (CMs) and a baseplate, where the baseplate is configured to communicate data signals via optical communication. Moreover, the array includes first CMs mechanically coupled to first alignment features on the baseplate, and adjacent second CMs mechanically coupled to second alignment features on the baseplate. In this array, a given first CM is electrically coupled to a given set of electrical proximity connectors. Additionally, the array includes bridge components, wherein a given bridge component is electrically coupled to the second SCM and another set of electrical proximity connectors, which is electrically coupled to the set of electrical proximity connectors, thereby facilitating communication of other data signals between adjacent first CMs and second CMs via electrical proximity communication. Moreover, the given bridge component is optically coupled to the baseplate, thereby facilitating optical communication of the data signals between CMs via the baseplate.

Multi-chip system including capacitively coupled and optical communication

Embodiments of a semiconductor die that includes proximity connectors proximate to a first surface of the semiconductor die are described. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. Moreover, the semiconductor die includes a positive feature coupled to a second surface of the semiconductor die that facilitates mechanical alignment of the semiconductor die with the other semiconductor die. Note that a first region around the positive feature defines a first plane, and the positive feature protrudes above the first plane.

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Palo Alto, CA, United States of America

James G Mitchell