Intel Corporation

James G Maveety

Gregory Martin Chrysler

Alan M Myers

Sarah E Kim

R Scott List

Quat T Vu

Unnikrishnan Vadakkanmaruveedu

Kramadhati V Ravi

Ravi S Prasher

Edward Rudolph Prack

Fay Hua

Thomas Dory

Ashish Gupta

Ioan Sauciuc

Ravi V Mahajan

John C Johnson

Gilroy J Vandentop

Michael L Rutigliano

Michael P Brownell

Abram M Detofsky

James Edward Neeb

James C Shipley

Tolga Acikalin

Christopher Wade Ackerman

Christopher Roy Schroeder

Ravindranath Vithal Mahajan

Eric DiStefano

Larry E Mosley

Himanshu Pokharna

Joe F Walczyk

Jin Yang

Todd P Albertson

Michael Zack Eckblad

Jin Pan

Michael C Garner

Arun Krishnamoorthy

Ronald Michael Kirby

William A Samaras

Joseph F Walczyk

Richard Michael Ramirez

Eduardo A Sanchez

Wayne Gaynor

George T Waller

A thermal controller includes a thermal control interface to receive test data from an automated test equipment (ATE) system and dynamically adjust a target setpoint temperature based on the data and a dynamic thermal controller to receive the target setpoint temperature from the thermal control interface and control a thermal actuator based on the target setpoint temperature.

Integrated circuit test temperature control mechanism

An apparatus to test a semiconductive device includes a base plane that holds at least one heat-transfer fluid unit cell. The at least one heat-transfer fluid unit cell includes a fluid supply structure including a supply-orifice cross section as well as a fluid return structure including a return-orifice cross section. The supply-orifice cross section is greater than the return-orifice cross section. A die interface is also included to be a liquid-impermeable material.

Direct liquid-contact micro-channel heat transfer devices, methods of temperature control for semiconductive devices, and processes of forming same

A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress.

Apparatus to minimize thermal impedance using copper on die backside

Embodiments of an apparatus and method for providing cooling of probes for testing of integrated circuits are generally described herein. In some embodiments, an apparatus comprises a probe head assembly configured to hold one or more probes that are adapted to provide electrical contact with an integrated circuit device under test (DUT), a DUT chuck adapted to hold the DUT for contact with the probes, a seal arranged between the probe head assembly and the DUT chuck to form a chamber when the seal is in contact with the probe head assembly and the DUT chuck, and a first port and a second port arranged to provide fluid flow into and fluid flow out of the chamber.

Seal method for direct liquid cooling of probes used at first level interconnect

A thermal interface unit includes a pedestal, a first contact surface below the pedestal to interface with a first die and a flat spring to enable the first contact surface to adapt to a variable height of a first die of a multi-chip package (MCP).

Thermal interface for multi-chip packages

The formation of electronic assemblies is described. In one embodiment, an electronic assembly includes a semiconductor die and a plurality of spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a fluid positioned between the spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a endcap covering the plurality of nanotube structures and the fluid, wherein the endcap is positioned to define a gap between the nanotube structures and an interior surface of the endcap. The endcap is also positioned to form a closed chamber including the working fluid, the nanotube structures, and the gap between the nanotube structures and the interior surface of the endcap.

Nanotube based vapor chamber for die level cooling

A structure including a die with at least one via within a semiconductor portion of the die, the via being proximate to a hot spot. The via is at least partially filled with a heat-dissipating material and is also capable of absorbing heat from the hot spot.

Die having a via filled with a heat-dissipating material

A carbon nanotube (CNT) array is patterned on a substrate. The substrate can be a microelectronic die or a heat sink for a die. The patterned CNT array is patterned by using a patterned catalyst on the substrate to form the CNT array by growing. The patterned CNT array can also be patterned by using a patterned mask on the substrate to form the CNT array by growing. A computing system that uses the CNT array for heat transfer from the die is also used.

Process that includes assembling together first and second substrates the have respective first and second carbon nanotube arrays with geometrically complementary patterns

A method, apparatus and system with a semiconductor package including a microchimney or thermosiphon using carbon nanotubes to modify the effective thermal conductivity of an integrated circuit die.

Carbon nanotube micro-chimney and thermo siphon die-level cooling

A semiconductor die is constructed and arranged to have at least one conduit portion therein. At least a portion of the conduit portion is proximate to the localized area. The conduit portion is at least partially filled with a heat-dissipating material. The conduit portion absorbs heat from the localized area and dissipates at least a portion of the heat away from the localized area.

Micro-chimney and thermosiphon die-level cooling

Process of making carbon nanotube array that includes impregnating the carbon nanotube array with metal

A thermal interface material is provided using composite particles. Advantages include increased thermal conductivity and improved mechanical properties such as lower viscosity. In selected embodiments free particles such as metallic particles or carbon nanotubes, etc. are included in a thermal interface material along with composite particles. An advantage of including free particles along with composite particles includes improved packing density within selected embodiments of thermal interface materials.

Thermal interface material with carbon nanotubes and particles

Growing community of inventors

San Jose, CA, United States of America

James G Maveety