Texas Instruments Corporation

James G Littleton

Michael D Asal

Richard D Simpson

Iain Craig Robertson

Jeffrey L Nye

Graham B Short

Michael A Denio

Jerry R Van Aken

William S Egr

Douglas C Crawford

Graham Short

An access circuit for data swapping between two computers and a computer system including the access circuit. Each computer including an address bus for supplying addresses and a data bus for transferring data. The access circuit includes a register file and two address decoder circuits. The register file has a plurality of storage locations for storing data. The register file has dual data ports capable of simultaneous data transfer via the first data port with a first data storage location and via the second data port with a second, different storage location. Each address decoder is connected to the address bus of a corresponding computer and the register file. The address decoders translate an address received on the address bus to a storage location of the register file. Two handshakes circuits are connected to respective address decoders and digital computers. The first and second address decoders are connected to each other. When the storage location of the first address decoder equals the storage location of the second address decoder, one of the handshake circuits signals the corresponding digital computer a memory waitstate or memory fault. At least one of the decoders is be programmable to position in the address space of the corresponding computer. At least one the address decoders includes an autoincrement circuit advances the accessed storage location within the register file to a next storage location upon each data transfer.

Two computer access circuit using address translation into common register file

A multifunction access circuit for use with first and second digital computers each having an address bus for supplying addresses and a data bus for supplying data. The access circuit has an address decoder with inputs for the address bus from the first computer, and an address translator circuit having address inputs for addresses supplied by the address bus of the first computer and outputs for translated addresses to the address bus of the second computer. The address translator circuit also has registers selectable by the address decoder and data inputs to program the registers so selected with data from the data bus from the first computer. Also in the access circuit is a port circuit with registers controlled by the address decoder for entry of address information from the data bus of the first computer and assertion of the address information on the address bus of the second computer. Further, a mode control circuit is connected to the address decoder and connected to the data bus to program the mode control circuit to selectively establish operation of the address translator circuit and of the port circuit. Other access circuits, devices, systems and methods are also described.

Multifunctional access devices, systems and methods

A computer graphics system includes a host computer and a graphics processor. The graphics processor includes a control register. When the graphics processor writes to the control register it simultaneously generates a predetermined address on a local address bus and supplies data on a local data bus identical to data to be written into the control register. A shadow register circuit connected to both the host computer and the graphics processor includes a shadow register and first and second address decoders. The first address decoder enables a write from a local data bus into the shadow register upon detection of the predetermined address. The second address decoder enables a read from the shadow register via a host data bus upon detection of the predetermined address on a host address bus. The shadow register optionally includes a message in plurality of bits and a message out plurality of bits, the first and second address decoders enabling message passing between the host computer and the graphics processor. The shadow register circuit optionally includes a host interrupt bit and a buffer circuit. The buffer circuit generates a host interrupt signal to the host computer if either the graphics processor generates a host interrupt signal or the host interrupt bit of the shadow register has a predetermined state.

Graphics processor writing to shadow register at predetermined address

A memory access system for use with a graphics processor having an address bus, a data bus and a set of control lines. An address translator circuit connected to the address bus of the graphics processor supplies a translated address to a memory upon receipt of an address from the graphics processor. A logic circuit responds to a write signal to automatically increment the translated address and responds to a control signal to return to the translated address. Control circuitry connected to the logic circuit responds to a read signal to supply the control signal to the logic circuit.

Memory access circuit with address translation performing auto increment

Apparatus and a method are disclosed for establishing communication between a sending system and a receiving system. Upon initiation of the communication, the sending system sequentially monitors the receiving system for a response from one of a human interface, a non-cooperating system or a cooperating system. If a response from a human interface within the receiving system is received by the sending system, the sending system transmits a message to a human. If a response is not received from a human interface but is received from a non-cooperating system within the receiving system, the sending system transmits a message to an answering machine. If a response is not received from a human interface or a non-cooperating system, but is received from a cooperating system within the receiving system, information is exchanged between the sending system and the cooperating system in an attempt to establish communication.

Telephone voice mail delivery system

A graphics computer system including a host computer and a graphics processor. The host computer has a host data bus and a host address bus. A first video memory stores color codes corresponding to a display. The first video memory is connected to the host computer permitting it to specify the color codes. A first palette connected to the first video memory has a first look-up table memory for recalling color data words corresponding to color codes received from the first video memory. The first palette is connected to the host computer permitting it to specify the color data words stored in the first look-up table memory. The graphics processor has a local data bus and a local address bus. A second video memory stores color codes corresponding to a display, the graphics processor specifying the color codes stored in the second video memory. A second palette connected to the second video memory has a second look-up table memory. The second palette is connected to the graphics processor permitting it to specify the color data words stored in the second look-up table memory. An interface circuit connects to the host data bus, the host address bus and the second palette. The interface circuit writes data received from the host data bus into the second palette upon detecting predetermined addresses on the host address bus. This causes at least a portion of the second palette to store identical data as stored in corresponding locations of the first palette.

Graphics computer system having a second palette shadowing data in a

A method is provided for adding extended functions to a multiprocessor system, specifically, functions that may be called from programming running on a first processor and executed by a second processor. The function may have an argument that requires a large amount of argument data. Each extended function is associated with a special entry point command, which is in turn, associated with a communications routine that handles the transfer of the large argument data from the first processor to the second processor in bursts.

First processor for dividing long argument data into packets and storing

An interface for use with a multiprocessor computer system, having a host processor system and a graphics processor system. The interface permits extended functions to be developed on the host system or on another system, and subsequently loaded to the graphics processor system. The interface comprises software residing on both the host system side and the graphics system side, which operates at run time to permit the function to be called from a main program running on the host. The function's arguments are passed to the graphics system so that the function is executed by the graphics processor.

Multiprocessor software interface for a graphics processor subsystem

A method used in a multiprocessor computer system for linking extended functions, which are to be called from an application program running on a host processor and executed by a subprocessor, to primitive functions to be executed by the subprocessor. The extended functions may be created independently of the primitive functions, collected in a special partially linked load module, stored, and dynamically linked to other code at run time of the application program.

Load time linker for software used with a multiprocessor system

A method for handling a cursor during a graphics drawing routine that eliminates the need to insert cursor handling code into graphics function definitions. The method coordinates the placement of the cursor in screen memory with the reading out of the scan lines containing the cursor. During this time, the cursor background is saved in offscreen memory. The cursor is protected by a cursor violation region, and drawing may continue while the cursor is in screen memory so long as the cursor violation region is not infringed, in which case drawing ceases until the cursor is read out of memory. The method prevents the cursor from flickering and maximizes the availability of screen memory to the drawing routine.

Graphics cursor handler

An adapter for modifying graphics software programs at load time. The invention is a process, which may be part of a hardware or firmware configuration used with a computer system, and which scans the program for selected instructions representing routines to be replaced with a substitute routine. If such an instruction is encountered, the instruction is replaced with an interrupt trap. The substitute graphics routine is located at an address stored at the interrupt trap location.

Growing community of inventors

Houston, TX, United States of America

James G Littleton