Motorola Corporation

James G Gilbert

John M Golio

Lawrence S Klingbeil, Jr

David J Halchin

Bertrand Francis Cambou

Thomas E Zirkle

Gregory L Hansell

Fourmun Lee

A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.

Method for fabricating an elevated-gate field effect transistor

A method of fabricating a MESFET is comprised of providing a semiconductor material having a channel region formed therein, forming a gate on the semiconductor material over the channel region, forming a spacer adjacent a first portion of the gate disposed on the semiconductor material, and forming a hard mask disposed on a second portion of the gate and on a portion of the semiconductor material.

Method of making symmetrical and asymmetrical MESFETS

Elevated-gate field effect transistor structure and fabrication method

A method for fabricating a sub-micron geometry semiconductor device using a chromeless mask. An optical exposure system (22) directs light through a chromeless mask (21). The chromeless mask (21) uses destructive interference of light to pattern a light sensitive material (32) on a semiconductor wafer (28). Phase differences in light passing thru chromeless mask (21) creates dark regions which form a non-exposed area of light sensitive material (37). The exposed light sensitive material is removed. The non-exposed area of light sensitive material (37) which remains, protects the gate material underneath it, as all other gate material is removed from the wafer. The non-exposed area of light sensitive material (37) is removed leaving a sub-micron gate (39). A drain and source is then formed to complete the device.

Fabrication method for a sub-micron geometry semiconductor device

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Tempe, AZ, United States of America

James G Gilbert