Cypress Semiconductor Corporation

Marvell Asia Pte., Ltd.

Flexsil, Inc.

James G Eldredge

Richard David Taylor

Ramacharan Sundararaman

Avinash Sodani

James R Nottingham

Nithyananda Miyar

Calvin K McDonald

R Samuel Lee

A new approach is proposed to support hardware-based update of a software (e.g., a firmware) of an electronic device in a non-functional state. Under the proposed approach, the software is stored securely on a resource (e.g., a non-volatile storge) protected by a hardware-based lock mechanism. A first agent acquires a lock and authenticate the software. When a boot failure (e.g. authentication of the software fails) of the electronic device happens, an alert indicating the failure is generated and sent to a second agent (e.g., a sideband master) through an alert mechanism. The second agent then acquires a lock from the hardware-based lock mechanism to obtain exclusive excess to the resource and update the software stored in the non-volatile storage through, e.g., block write and/or read operations. The second agent then verifies that the software has been updated successfully so that the electronic device becomes functionally again.

System and methods for firmware update mechanism

A system includes a power profile engine, a power measurement engine, and a power throttling signal generator. The power profile engine receives a desired power profile, e.g., a first profile current average associated with a first time duration and a second profile current average associated with a second time duration. The power measurement engine measures current being drawn and generates a first running average for the measured currents for the first time duration and generates a second running average for the measured currents for the second time duration. The power throttling signal generator generates a first power throttling signal to throttle power in response to the first running average for the measured currents being greater than the first profile current average and generates a second power throttling signal to throttle power in response to the second running average for the measured currents being greater than the second profile current average.

System and method to manage power to a desired power profile

A power converter capable of providing a range of DC voltages to an external device and a method of providing a range of DC power are provided. The power converter comprises a supply circuit for receiving a request for DC power and for providing the requested DC power. The supply circuit comprises a detection circuit for sensing a connection to an external device, a source controller circuit for determining a DC output power required by the external device, and a converter circuit for generating the required DC output power. The external device comprises a device controller circuit for communicating the request for DC power. A first conductor provides a path for the device to communicate the required DC power to the power converter and for the power converter to supply the required DC power. A second conductor provides a common reference for conducting return current to the power converter.

Universal DC power

Peer-to-peer Direct Memory Access (DMA) permits the efficient transfer of data from one DMA capable Application Specific Integrated Circuit (ASIC) block to another without accessing memory. The peer-to-peer transfer can be done over a standard AMBA AHB bus architecture without side band signals and without violating the AHB specification.

Efficient peer-to-peer DMA

An interpolation scheme uses cubic subdivision to index a position of an input color value in a color space relative to neighboring vertices. The indexed position of the input color value is expanded and the neighboring vertices are combined together according to the expanded index to generate an output color value.

Apparatus and method for color data interpolation

A microprocessor system is provided that includes a first memory bank having a first base address and a second memory bank having a second base address. A memory controller is adapted to register the first and second base addresses. A swap command is adapted to instruct the memory controller to swap the first and second base addresses. A microprocessor issues the swap command. The memory controller includes a first base address register adapted to register the first base address and a second base address register adapted to register the second base address. A command register is adapted to register the swap command. In one embodiment, the first memory bank is a DRAM bank and the second memory bank is a ROM bank. The swap command instructs the memory controller to swap the first and second base addresses before temporary storage is established in the DRAM bank.

Dynamic swapping of memory bank base addresses

A color data converter includes a plurality of memories configured to store lattice points for a color space. The lattice points of the first axis are assigned to memories in a sequential manner. The lattice points along the other two axes are assigned to memories in an alternating manner.

Growing community of inventors

Meridian, ID, United States of America

James G Eldredge