International Business Machines Corporation

James G Brenza

Casper A Scalzi

Kathryn Marie Jackson

Joseph M Gdaniec

Peter H Gum

Bhaskar Sinha

Mark M Maccabee

An addressing method using large addresses in a guest/host environment within a computer system. The guests are operating-systems, and the host is a hypervisor program. Each guest has a guest real address space (guest RAS) mapped onto a host large real address space (host LRAS) using means disclosed herein. To do this, each guest RAS is first assigned to a contiguous part of a host large virtual address space (LVAS) by assigning each guest RAS to one or more contiguous units of virtual addressing in the host LVAS, each unit having a 2 gigabyte (GB) size. The host LVAS is represented by a sequence of entries (ALEs) in a host access list (AL), in which each ALE represents a 2 GB unit of virtual addressing in the host LVAS. An ALE is selected in the AL by using a high-order part of a host large virtual address (host LVA) representing a guest RA or LRA. A host LVA is generated from a guest RA for obtaining the guest address in host main storage. The host LVA is translated in a number of different ways to a host LRA, depending on the type of guest providing the corresponding guest RA or LRA. The guest types include V=V, V=FC, V=FD and V=R guests, which is indicated in a guest control block (GCB).

Guest/host extended addressing method and means with contiguous access

A CPU has N-1 ports for concurrently making memory requests and transferring data using a cache with M partitions. Each partition includes a cache directory partition and a corresponding cache data store partition. Each port has a Partition Look-Aside Table (PLAT). Each PLAT has multiple entries that store the most-recent valid memory requests made by its CPU port. A PLAT entry includes a cache partition identifier, a control field, and a congruence-class address for locating associated data in the identified partition. Simultaneous cache accessing in up to N-1 different partitions may be made by N-1 CPU requests have PLAT local hits. The Nth port services global cache misses. An address switch simultaneously connects the CPU requests to up to N different partitions. A PLAT 'local hit' occurs when a CPU request equals PLAT valid entry, enabling immediate accessing of the requested data in the identified partition. A PLAT 'miss' generates a 'global' request sent to all partitions. If the global request is found in any partition, a global 'hit' occurs, and the data is transferred to the requesting CPU port through a data bus switch, and the port's PLAT is validated. If the global request is not found in any partition, a global 'miss' occurs, which is sent to the system memory hierarchy for a data fetch; LRU circuits select a partition for receiving the data fetch, and a new PLAT entry is generated for the requesting port.

Partitioned cache memory with partition look-aside table (PLAT) for

A data processing system which contains a multi-level storage hierarchy, in which the two highest hierarchy levels (e.g. L1 and L2) are private (not shared) to a single CPU, in order to be in close proximity to each other and to the CPU. Each cache has a data line length convenient to the respective cache. A common directory and an L1 control array (L1CA) are provided for the CPU to access both the L1 and L2 caches. The common directory contains and is addressed by the CPU requesting logical addresses, each of which is either a real/absolute address or a virtual address, according to whichever address mode the CPU is in. Each entry in the directory contains a logical address representation derived from a logical address that previously missed in the directory. A CPU request 'hits' in the directory if its requested address is in any private cache (e.g. in L1 or L2). A line presence field (LPF) is included in each directory entry to aid in determining a hit in the L1 cache. The L1CA contains L1 cache information to supplement the corresponding common directory entry; the L1CA is used during a L1 LRU castout, but is not the critical path of an L1 or L2 hit. A translation lookaside buffer (TLB) is not used to determine cache hits. The TLB output is used only during the infrequent times that a CPU request misses in the cache directory, and the translated address (i.e. absolute address) is then used to access the data in a synonym location in the same cache, or in main storage, or in the L1 or L2 cache in another CPU in a multiprocessor system using synonym/cross-interrogate directories.

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Putnam Valley, NY, United States of America

James G Brenza