Psemi Corporation

Other

International Business Machines Corporation

Javelin Semiconductor, Inc.

James Francis McElwee

Tero Tapio Ranta

Emre Ayranci

Miles Sanner

Chih-Chieh Cheng

Kevin Roberts

Ke Li

Hayden C Cranford, Jr

John James Paulos

Eric Kimball

Magesh Valliappan

Ronald Steven Gyurcsik

A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability. In a third version, CA direct mapped adaptive tuning networks include filter tuning blocks for selected lower frequency bands.

Adaptive tuning networks with direct mapped multiple channel filter tuning

In one embodiment, a method includes generating a first current in a bias current circuit and biasing an amplifier with the first current when the amplifier is operating in a first temperature range, and generating a second current in the bias current circuit and biasing the amplifier with the second current when the amplifier is operating in a second temperature range. These two currents may correspond to different profiles with respect to temperature, to maintain substantial linearity of the amplifier over the temperature ranges.

Providing a temperature dependent bias for a device

GBit/s transceiver with built-in self test features. A method is disclosed for testing the operation of a transceiver having a digital processing section and an analog section, each having a transmit portion and a receive portion, the analog portions adaptable to interface with an analog network. The transceiver is first configured to operate in a test mode. In the test mode, the transmit portion of the digital processing section is activated to generate data to be transmitted by the transmit portion of the analog section. The receive portion of the analog section and the receive portion of the digital processing section are operated to receive data. Thereafter, the parametrics of select portions of the receive portion of the digital processing section are examined during the receipt of data by the receive portion of the analog section and processing thereof by the receive portion of the digital processing section.

GBit/s transceiver with built-in self test features

A low voltage CMOS multiplier uses a transconductance stage to generate a dynamic bias current which is used to compensate for non-linear terms in a Gilbert Cell multiplier circuit. Common mode dependence is minimized by using balanced differential input stages for both the transconductance and multiplier stages.

Low voltage CMOS analog multiplier with extended input dynamic range

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Austin, TX, United States of America

James Francis McElwee