Micron Technology Incorporated

Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Quantum Corporation

Smart Storage Systems, Inc.

Sandisk Enterprise IP LLC

Seagate Technology Incorporated

Maxtor Corporation

James Fitzpatrick

Sivagnanam Parthasarathy

Patrick Robert Khayat

Kishore Kumar Muchherla

Abdelhakim Alhussien

James M Higgins

AbdelHakim S Alhussien

Phong Sy Nguyen

Mark Joseph Dancho

Robert W Ellis

Akira Goda

Dung Viet Nguyen

Huai-Yuan Tseng

Violante Moschiano

Eric N Lee

Mostafa El Gamal

Tomoharu Tanaka

Niranjay Ravindran

Jeffrey S McNeil, Jr

Bernardo Rub

Dave Scott Ebsen

Mustafa Nazmi Kaynak

Sanjay Subbarao

Vamsi Pavan Rayaprolu

Mark Alan Helm

Jiahui Yuan

Henry Chin

Richard David Barndt

Daniel J Hubbard

Ravi J Kumar

Ryan R Jones

Giovanni Maria Paolucci

Bernie Rub

Li Li

Sampath K Ratnam

Sergey Anatolievich Gorobets

Nian Niles Yang

Karl David Schuh

Jiangang Wu

Niles Yang

Ugo Russo

David Scott Ebsen

Xinmiao Zhang

Amirhossein Rafati

Ashutosh Malshe

Ara Patapoutian

Bruce Douglas Buch

Jung Sheng Hoei

Steven Theodore Sprouse

Daniel Lee Helmick

Michele Incarnati

Amir Shaharabany

Aaron Keith Olbrich

Jeremy Binfet

Hadas Oshinsky

Walter Di Francesco

Giuseppina Puzzilli

Kevin Dean Fisher

Umberto Siciliani

Niccolo' Righetti

Yacov Duzly

Neil Richard Darragh

Peter A McEwen

Niccolo′ Righetti

Bill Richard Baker

Tecla Ghilardi

Amir Hossein Gholamipour

Sead Zildzic

Xiaodong Che

Sheunghee Park

Bahjat Zafer

Christopher Montgomery Carpenter

Michelle Martin

Yiwei Song

Mervyn Wongso

George H Bellesis

Shyam Sunder Raghunathan

Robert A Johnson

James M Kresse

Tzuochang Lee

Leo Guglielmo

Kelly J Knudson

James R Tylock

Kishore Kumar Muccherla

Robert Steven Burns

Jennifer Stander

Padmanabhan Srikrishna

Jason Henry

Ken DelPapa

John Scaramuzzo

Systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. The control logic can perform operations comprising causing a read operation to be initiated with respect to a set of target cells of the memory array; obtaining, for a respective group of adjacent cells, respective cell state information; performing a set of strobe reads on the set of target cells; and generating, for a target cell of the set of target cells, semi-soft bit data based on the respective cell state information of the respective group of adjacent cells and on data obtained from a first strobe read and a second strobe read of the set of strobe reads performed on the target cell.

Generating semi-soft bit data during corrective read operations in memory devices

A processing device in a memory sub-system detects an occurrence of a data integrity check trigger event and, responsive to the occurrence of the data integrity check trigger event, identifies a memory die of a plurality of memory dies. The processing device further associates each segment of the identified memory die with a respective group of a plurality of groups, each group representing one or more of a plurality of error mechanisms, and determines one or more respective adaptive scan frequencies for the identified memory die based on statistics of the segments associated with each respective group.

Adaptive integrity scan rates in a memory sub-system based on block health metrics

Exemplary methods, apparatuses, and systems include an adaptive pre-read manager for controlling pre-reads of the memory device. The adaptive pre-read manager receives a first set of data bits for programming to memory. The adaptive pre-read manager performing a first pass of programming including a first subset of data bits from the set of data bits. The adaptive pre-read manager compares a set of threshold operating differences to a set of differences between multiple operating conditions during the first pass of programming and current operating conditions. The adaptive pre-read manager performs an internal pre-read of the programmed first subset of data bits. The adaptive pre-read manager performs a second pass of programming using the internal pre-read and a second subset of data bits from the first set of data bits.

Adaptive pre-read management in multi-pass programming

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies the threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and causing the memory device to copy data the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.

Memory compaction management in memory devices

A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Adjustment of code rate as function of memory endurance state metric

A method includes causing a first set of memory cells, associated with a first wordline of a memory array, to be programmed with a first set of threshold voltage distributions; causing a second set of memory cells, associated with a second wordline adjacent to the first wordline, to be programmed with a second set of threshold voltage distributions; after programming the second set of cells, causing the first set of memory cells to be coarse programmed with an intermediate third set of threshold voltage distributions that is at least twice in number compared to the first set; and causing the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions. At least some threshold voltage distributions of the final third set of threshold voltage distributions have wider read window margins than those of the intermediate third set of threshold voltage distributions.

Memory programming using consecutive coarse-fine programming operations of threshold voltage distributions

A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

Memory device programming technique for increased bits per cell

A set of data items programmed to a first region of a memory subsystem is identified. The set of data items is programmed to the first region according to an initial sequence. A determination is made of whether the initial sequence corresponds to a target sequence associated with accessing the set of data items. Responsive to a determination that the initial sequence does not correspond to the target sequence, the set of data items is copied from the first region to a second region of the memory subsystem according to the target sequence.

Data reordering at a memory subsystem

A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices

A method includes causing a read operation to be initiated with respect to a set of target cells. For each target cell, a respective group of adjacent cells is adjacent to the target cell. The method further includes obtaining, for each group of adjacent cells, respective cell state information, assigning, based on the cell state information, each target cell of the set of target cells to a respective state information bin, and determining a set of calibrated read level offsets. Each state information bin is associated with a respective group of target cells of the set of target cells, and each calibrated read level offset of the set of calibrated read level offsets is associated with a respective state information bin of the set of state information bins.

Conditional valley tracking during corrective reads

Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

Apparatus with non-linear delay variations for scheduling memory refresh operations and methods for operating the same

A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.

Determine optimized read voltage via identification of distribution shape of signal and noise characteristics

A memory device comprising an array of memory cells organized into a set of sub-blocks and a set of wordlines. Control logic is operatively coupled with the array of memory cells, the control logic to perform operations including: receiving a program command from a processing device, the program command including information indicative of a physical address associated with a retired wordline of the set of wordlines; in response to detecting the information within the program command, generating dummy data that is one of pseudo-random data, all one values, or all zero values; and causing the dummy data to be programmed to memory cells of multiple sub-blocks of the set of sub-blocks that are selectively connected to the retired wordline.

Program command generation with dummy data generation at a memory device

Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

Quick charge loss mitigation using two-pass controlled delay

A method includes receiving, by control logic of a memory device, a copyback clear command from a processing device; causing, in response to the copyback clear command, a page buffer to perform a dual-strobe read operation on first memory cells configured as single-level cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage that are sensed between threshold voltage distributions of the first memory cells; causing the page buffer to determine a number of one bit values within the threshold voltage distributions detected in a threshold voltage range between the first/second threshold voltages; and causing, in response to the number of one bit values not satisfying a threshold criterion, a copyback of data in the first memory cells to second memory cells configured as high-level cells without intervention from the processing device.

Copyback clear command for performing a scan and read in a memory device

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Laguna Niguel, CA, United States of America

James Fitzpatrick