Texas Instruments Corporation

Other

James F Potts

Jerald G Leach

L Ray Simar, Jr

Surendar S Magar

Steven P Marshall

Bimal Pathak

L Ray Simar Jr

A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus.

Data processing device with time-multiplexed memory bus

A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxilary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus. Memory-mapped input and output functions are performed by on-chip peripherals, which are connected to a peripheral bus connected to one of the peripheral ports of the microcomputer. The peripheral bus allows for substantial flexibility relative to the configuration of the microcomputer.

Data processing device with multiple on-chip memory buses

A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus. Memory-mapped input and output functions are performed by on-chip peripherals, which are connected to a peripheral bus connected to one of the peripheral ports of the microcomputer. The peripheral bus allows for substantial flexibility relative to the configuration of the microcomputer.

Data processing device with improved direct memory access

A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme. If the calculated memory address is outside of the block limits, an adder/subtractor in the auxiliary arithmetic logic units either adds or substracts the block size to or from the calculated memory address, so that the result is an address at the other end of the block. The result of the calculation, whether or not modified, is stored in a memory address register. The pair of auxiliary arithmetic logic units are operable in parallel with each other, and in parallel with the primary arithmetic logic unit. The two memory addresses are presented to the on-chip memory in time-multiplexed fashion, so that two memory accesses may be performed in a single machine cycle.

Data processing device with parallel circular addressing hardware

A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microprocessor has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxillary arithmetic logic units, in parallel with one another, and which are each connected to a set of address lines in a memory bus; the two auxillary arithmetic logic unit thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle. A second memory bus is also connected to the on-chip RAM and ROM, and to the peripheral ports, so that access to one of the memory elements via said first memory bus can occur simultaneously with, and independently from, access to another of said memory elements via said second memory bus. The on-chip memory and external memory are all mapped into a single memory address space, which allows simultaneous program and data fetches via the two memory buses, or a program and data fetch during the same cycle using the first time-multiplexed bus. Memory-mapped input and output functions are performed by on-chip peripherals, which are connected to a peripheral bus connected to one of the peripheral ports of the microcomputer. The peripheral bus allows for substantial flexibility relative to the configuration of the microcomputer.

Data processing device with multiple on chip memory buses

A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme. If the calculated memory address is outside of the block limits, an adder/substractor in the auxiliary arithmetic logic units either adds or subtracts the block size to or from the calculated memory address, so that the result is an address at the other end of the block. The result of the calculation, whether or not modified, is stored in a memory address register. The pair of auxiliary arithmetic logic units are operable in parallel with each other, and in parallel with the primary arithmetic logic unit. The two memory addresses are presented to the on-chip memory in time-multiplexed fashion, so that two memory accesses may be performed in a single machine cycle.

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Houston, TX, United States of America

James F Potts