Lucent Technologies Inc.

Lattice Semiconductor Corporation

Gte Communication Systems Corporation

Ag Communication Systems Corporation

James F Hoff

Randall L Brown

John Spenik

Satwant Singh

Thomas J Perry

Barry Britton

Zheng Chen

John S Young

Richard G Stuby, Jr

John Wesley Spenik

William B Andrews

Frank Sciabica

Christopher A Pawlowski

James B Southway, Jr

Arthur L Walsh

Ravikumar Charath

Ju-Yuan D Yang

Don McCarley

Cort D Lansenderfer

Thomas J Buege

Keith M McDonald

Kevin B Plyler

Satrio P Mualim

Scott J Baer

Kevin B Plyer

James B Southway

John W Spenik

A system that provides additional voice lines with data over a single two-wire subscriber loop. At the subscriber premise, one or more telephone instruments and data devices are connected to a digital modem into either a voice or a data interface. Analog voice signals are PCM sampled then packetized, and voice and data packets are transmitted to a CO modem over the subscriber loop. The CO modem depacketizes the voice packets into PCM format and transmits PCM voice information to a CO switch over a standard digital trunk interface. Data packets are routed to a data network. Voice packets are given transmission priority over data packets to ensures that voice is transported in the presence of data with low latency.

System for multiple voice lines with data over a single subscriber loop

An embedded system bus is woven between a plurality of embedded master elements and at least one slave element within the FPGA device, and provides an external processor interface allowing direct access to any of the plurality of embedded slave elements. Using the embedded system bus, any of a plurality of masters may be allowed to program an embedded element, e.g., embedded FPGA logic, whereas conventional FPGAs allowed only a single master (e.g., a processor) to program the embedded FPGA logic. The embedded system bus is a group of signals, typically data, address and control, that connects system elements together and provides a basic protocol for the flow of data. The embedded system bus allows for control, configuration and status determination of the FPGA device. The embedded system bus is preferably a dedicated function available at all times for arbitrated access to allow communication between the various embedded system components.

Multi-master multi-slave system bus in a field programmable gate array (FPGA)

A field-programmable gate array (FPGA) having at least one programmable cell (e.g., an input/output (I/O) cell) having an output node circuit (e.g., a pad circuit) in which the output data signal and the tri-state signal are applied to a multiplexer that drives the tri-state port of an output buffer in the output node circuit. This configuration enables the output node circuit to be configured for open drain drive mode operations in a fast, predictable manner that does not need to rely on the FPGA's general routing resources.

FPGA having predictable open-drain drive mode

A system that provides secure transmission of data between a subscriber's PC and an online service provider (OLS) over an Ethernet WAN. The system includes a remote transceiver unit located at a subscriber site and connected to the subscriber's PC; a central transceiver unit located at a telephone central office and connected to the remote transceiver unit over a twisted pair network and also connected to a WAN; an authorization server that is connected to the WAN; and one or more OLSs, which may include Internet service providers, connected to the WAN. Security of transmission is provided through a method in which only subscriber transmissions directed to a session-specific OLS are allowed to pass through the central transceiver unit onto the WAN, and only unicast transmissions from authorized OLSs are allowed to pass through the central transceiver unit to the subscriber port of the remote transceiver unit. Broadcast transmissions are minimized in favor of unicast messages. The authorization server delivers the IP and MAC addresses of the session-specific OLSs and the subscriber's PC to the remote transceiver units.

Wide area network system providing secure transmission

An echo cancellation arrangement is provided for decreasing the 'singing' of a connection of a large number of telephone subscribers in a conference calling arrangement. This arrangement includes a means for inserting quiet code during time when the voice samples of incoming PCM data are zero or below a predetermined minimum threshold level. This helps decrease the amount of feedback which is amplified and output through the codec/filter to the listeners through the PCM network. An attenuation arrangement is also included which decreases the level of a summed signal of a summing node of the conference circuit. This sum signal is the combination of each of the conferees' speech. Attenuation of this signal prohibits excessive coupling of amplified feedback to each of the listening conferees.

Digital voice switch for a multi-port conference circuit

Growing community of inventors

Bethlehem, PA, United States of America

James F Hoff