General Electric Company

James F Burgess

Constantine A Neugebauer

Homer H Glascock, Ii

Victor A Temple

Donald L Watrous

Raymond Albert Fillion

Harold F Webster

Robert J Satriano

Charles Dominic Iacovangelo

Sayed-Amr A El-Hamamsy

Steven Marc Gasworth

Charles S Korman

Otward M Mueller

Donald W Jones

Eric J Wildi

James A Loughran

Michael W DeVre

Roland T Girard

Francois D Martzloff

Walter M Bryant

Guy L Babcock

Wivina A DeDoncker

A power device component package includes a substrate supporting a drain lead, a source lead, and a gate lead. Each of the leads comprises an electrically conductive material having a thickness sufficient to form a high current contact. A power device component with component pads has an electrically conductive backside supported by and electrically coupled to the drain lead. A dielectric layer overlies at least portions of the component, the source lead, and the gate lead and has a plurality of vias therein aligned with predetermined ones of the component pads and predetermined portions of the source and gate leads. A pattern of electrical conductors extends through selected ones of the vias, with a first portion of the pattern coupling selected ones of the component pads to the source lead and a second portion of the pattern coupling at least one other of the component pads to the gate lead.

Wireless radio frequency power semiconductor devices using high density

Power semiconductor device structures and assemblies with improved heat dissipation characteristics and low impedance interconnections include a thermally-conductive dielectric layer, such as diamondlike carbon (DLC) overlying at least portions of the active major surface of a semiconductor chip, with vias formed in the dielectric layer in alignment with contact pads on the active major surface. A patterned metallization layer is formed over the thermally-conductive dielectric layer, with portions of the metallization layer extending through the vias into electrical contact with the chip contact pads. A metal structure is electrically and thermally coupled to selected areas of the patterned metallization, such as by solder bonding or by a eutectic bonding process. In different embodiments, the metal structure may comprise a metal conductor bonded to the opposite major surface of another power semiconductor device structure, a heat-dissipating device-mounting structure, or simply a low-impedance lead.

Direct stacked and flip chip power semiconductor device structures

Differences in thermal expansion properties between integrated circuit chips, especially of gallium arsenide, and the dielectric substrates (especially diamond and aluminum nitride) on which said chips are mounted are accommodated by interposing between the substrate and the chip a base having diamond pedestals in combination with a material of higher coefficient of thermal expansion than the substrate, typically a metal such as copper or tungsten. The base may be integral with a diamond substrate or may be a shim interposed between the substrate and the chip.

Electronic apparatus with improved thermal expansion match

An integrated heat sink module includes a sinuously channeled base and a bonded top surface electrode that is dielectrically isolated from the base. The top surface electrode acts as a common modular electrode capable of conducting heat to an ultimate cooling medium with no intervening thermal barrier. Constrained copper technology (CCT) is employed to ensure that the relatively low effective temperature coefficient of expansion of the channel base is acquired by the channel cover, which is the dielectrically (but not thermally) insulated top surface, and that the common electrode is integrated with, by forming a part of, the fluid channel in the base. The heat sink weight is reduced significantly by the channeling, while use of the CCT technology ensures high reliability and integrity of the module.

Integrated heat sink having a sinuous fluid channel for the thermal

A hermetic semiconductor package having a ceramic lid with the device leads extending vertically through the lid is disclosed. The leads are mechanically retained within the apertures in the lid and direct bonded to the lid to provide a hermetic seal and a substantial lead density.

Hermetic package and packaged semiconductor chip having closely spaced

A hermetic semiconductor package includes a ceramic lid with the device leads extending vertically through the lid. The leads are mechanically retained within the apertures in the lid and direct bonded to the lid to provide a hermetic seal and a substantial lead density.

A hermetically sealed package for a semiconductor device includes a lid through which the leads of the device extend vertically away from the chip through an aperture in the lid which is hermetically sealed by the external terminal or electrode. The package is compact, lightweight and free of magnetic materials.

Method of forming a hermetic package having a lead extending through an

A hermetic, high current package for a semiconductor device includes wide flat leads which are bonded to the contact pads of the device and formed to extend through apertures in an insulating lid. The lid is sealed to a base and the apertures around the leads are sealed with solder to provide the hermetic package. This package limits lateral current flow in the contact pads of the semiconductor device to relatively low levels which ensure the integrity of the contact pads.

Method of packaging a semiconductor chip in a low inductance package

Hermetic package having a lead extending through an aperture in the

A composite structure comprising a symmetric bimetallic laminate bonded to a separate substrate is provided by eutectic bonding the bimetallic laminate to the substrate. A variety of beneficial structures can be provided.

Direct bonded symmetric-metallic-laminate/substrate structures

High current hermetic package having a lead extending through the

A direct (metal-metal compound eutectic) bond process is improved by disposing a eutectic/substrate-wetting enhancement layer on the substrate prior to performing the direct bond process to bond a metal foil to the substrate. Where the metal is copper, the direct bond process is rendered more effective than prior art direct bond processes on alumina and beryllia and makes the direct bond process effective on tungsten, molybdenum and aluminum nitride, all of which were unusable with the prior art direct bond copper process. A variety of new, useful structures may be produced using this process. The eutectic/substrate-wetting enhancement layer is preferably a noble-like metal or includes a noble-like metal such as platinum, palladium and gold.

Enhanced direct bond structure

Multilayer circuit boards composed primarily of silicon and containing buried ground planes and buried conducting runs are fabricated in one embodiment by positioning conductive patterns (12) on the surfaces of silicon substrates and melting a solder component of the conductive patterns (12) and allowing it to flow together with solder from the conductive patterns (12) on a stacked, adjacent silicon substrate (10). When the solder cools, a single conductive pathway (18) exists between adjacent silicon substrates (10) and bonds the adjacent substrates. If the substrates are coated with SiO.sub.2 (20), a multilayer structure with buried microwave strip lines (22) is formed in the bonding process. Alternatively, highly resistive silicon substrates (26) are used as a dielectric for microwave strip lines (24) on a top surface thereof and a conductive sheet (28) on the bottom surface thereof acts as a ground plane for microwave energy propagating along strip line (24).

Multilayer circuit board fabricated from silicon

A circuit board assembly for supporting a leadless ceramic chip carrier for surface mounting on a printed circuit board and for reducing the thermally induced stress on solder joint connections at the carrier-to-board contacts. The board includes an inner heat sink core comprising a highly conductive plate having openings provided therein in the areas which underlie the chip carrier. The openings have inserts therein of a material which closely matches the thermal coefficient of expansion of the ceramic to thereby reduce stress of the intermediate solder joints.

Circuit board construction

Reconstituted metal oxide varistors are formed by hot pressing powdered metal oxide varistor ceramic with plastic resin. Metal electrodes may be pressed directly into the ceramic-plastic composite to provide improved contact characteristics.

Growing community of inventors

Schenectady, NY, United States of America

James F Burgess