Nec Corporation

Zenith Data Systems Corporation

Packard Bell Nec

Bull Hn Information Systems, Inc.

James F Bertone

Thomas F Joyce

Jian-Kuo Shen

Chester M Nibby, Jr

Bruno DiPlacido, Jr

Jeffrey S Somers

Thomas L Murray, Jr

Michelle A Pence

G Lewis Steiner

Martin Massucci

Marc Sanfacon

Lance J McNally

William S Wu

Suresh K Marisetty

Norman J Rasmussen

Puthiya K Nizar

David E Cushing

Elmer W Carroll

Edward Hutchings

Lance T McNally

Robert A Coelho

Lewis G Steiner

Bruno Diplacido

Lance Mcnally

The invention is directed to a memory controller for use with memory having varying timing characteristics. In particular, the timing characteristics of the various memory devices are determined and used to generate timing signals commensurate with each particular memory device.

Symmetric multiprocessing system with unified environment and distributed system functions

A graphical user interface provides a navigation model in the form of a hierarchical tree structure which is representative of a server system a user selected to manage. The hierarchical tree structure is populated or built to include a number of icons representative of different classes or categories of major components and their associated subcomponents contained in the selected server system and their logical relationships. In response to user icon selections, the navigation model expands and collapses the tree structure in a predetermined manner so as to enable the user to easily navigate through the different levels of components and subcomponents of the server with a minimum amount of information and determine status in addition to setting threshold values for items to be managed within the server system.

Graphic user interface for managing a server system

A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

Symmetric multiprocessing system with unified environment and

Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.

Adaptively generating timing signals for access to various memory

In a data processing system, a data processing unit contains data processing logic including shadowed functional registers for storing the data being processed. The units also include fault monitoring logic, including, for each shadowed functional register, a shadowing copy register connected in parallel from the corresponding shadowed register to receive and store a copy of the data resident in the shadowed register. Test logic is connected from the shadowed and shadowing registers for comparing the data resident in the shadowed and shadowing registers and providing indications of possible faults in the data processing logic. The shadowed and shadowing registers are connected in a serial scan chain through a serial scan data path. The integrity of the fault monitoring logic is tested by serially shifting, or scanning, known test patterns of bits through the serial scan chain comprised of the shadowed registers and shadowing registers. A first set of patterns are selected so that the test patterns themselves should not induce any errors to appear to the comparison logic so long as the the test logic is correct, so that any errors that are detected are due to a fault in the test logic. A second set of test patterns are selected to induce errors to appear as the patterns are shifted, bit by bit, through the scan chain. The first patterns thereby determine that there are not errors in the fault monitoring logic itself, and the second patterns that the fault monitoring logic is detecting errors correctly.

Method and apparatus for integrity testing of fault monitoring logic

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Quincy, MA, United States of America

James F Bertone