International Business Machines Corporation

Intel Corporation

Other

James Edward Phillips

Stamatis Vassiliadis

Susan Elizabeth Eisen

Bartholomew Blaner

James D Allen

Wing Shek Wong

David Allen Hrusecky

Venkateswara Rao Madduri

Rajesh Bhikhubhai Patel

Vincent Charles Conzola

Belliappa Manavattira Kuttanna

Robert L Farrell

Glen Howard Handlogten

Jonathan D Combs

Martin Stanley Schmookler

Chuck Hong Ngai

Stephen J Robinson

Dennis P Cheney

Lawrence Joseph Powell, Jr

Scott E Siers

Andrew Augustus Bjorksten

Jonathan Jay Tyler

Raymond J Eberhard

Kameswar Subramaniam

Deepak Limaye

Richard E Fry

T W Griffith

Charles Vitu

Kulin N Kothari

Richard T Pfeiffer

Duc Quang Bui

George Quyen Phan

Jerome J Cassellius

A processor includes a core and a scheduler. The scheduler includes first and second dependency matrices and a ready determination unit. The scheduler also includes logic to queue a first parent operation, a second parent operation, and a child operation that includes first and second sources dependent on the first and second parent operations. The scheduler also includes logic to store physical addresses of the first and second sources of the child operation respectively in the first and second dependency matrices. Further, the scheduler includes logic to perform a tag comparisons between the respective physical addresses of the destinations of the first and second parent operations respectively with the respective physical address of the first and second sources of the child operation. In addition, the ready determination unit includes logic to determine that the child operation is ready for dispatch based on the tag comparisons.

Instruction and logic for a matrix scheduler

A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.

Micro-architecture for eliminating MOV operations

In an embodiment, a processor includes a plurality of cores. Each core includes conversion power logic to receive an instruction including an untranslated memory address, determine whether a code segment (CS) base address is equal to zero, and in response to a determination that the CS base address is equal to zero, execute the instruction using the untranslated memory address. Other embodiments are described and claimed.

Power logic for memory address conversion

An apparatus including an execution logic that includes circuitry to execute instructions, and an instruction execution scheduler logic coupled with the execution logic. The instruction execution scheduler logic is to receive an execute at commit state update instruction. The instruction execution scheduler logic includes at commit state update logic that is to wait to schedule the execute at commit state update instruction for execution until the execute at commit state update instruction is a next instruction to commit. Other apparatus, methods, and systems are also disclosed.

Execute at commit state update instructions, apparatus, methods, and systems

Methods and apparatus relating to dynamic selection of execution stage are described. In some embodiments, logic may determine whether to execute an instruction at one of a plurality of stages in a processor. In some embodiments, the plurality of stages are to at least correspond to an address generation stage or an execution stage of the instruction. Other embodiments are also described and claimed.

Dynamic selection of execution stage

Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.

Methods and apparatus for address generation in processors

An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent 'pipes' from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the 'fpr target') are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand. In this situation, the mechanism prioritizes the first of the two instructions to be issued to the pipe satisfying the dependency, while the second instruction is preempted in favor of issuing an independent instruction or an instruction whose dependent data has already been made available to the other pipe when such an instruction is waiting in a queue.

Data processing system and method for implementing an efficient out-of-order issue mechanism

During execution of floating point convert to integer instructions, the necessity for incrementing the instruction result during rounding is predicted early and utilized to predict the result sign, to produce an implied bit which will achieve the correct result with round determination logic for standard floating point instructions, and to set up rounding mode, guard and sticky bits allowing the standard round determination logic to be utilized during rounding of the floating point convert to integer instruction result. The minimum logic required to control incrementing of a standard floating point instruction result during rounding may therefore be reused for floating point convert to integer instructions without increasing the critical path for rounding and without significantly adding to the complexity of the floating point execution unit.

Method and predictor for streamlining execution of convert-to-integer operations

A method for wrap detection in a microprocessor system, the system including a plurality of rename buffers. The method includes performing a two's complement subtraction of a completion pointer from a target pointer, wherein a carry out results from the subtraction. The method further includes comparing the carryout and a virtual bit associated with a location to produce a result. The result is compared to the most significant bit of the target pointer and if there is a match between the most significant bit of the second pointer and the result, an indication is made that the instruction may issue. A system for utilizing the above method of wrap detection includes a means for performing a two's complement subtraction of a completion pointer from a target pointer, wherein a carry out results from the two's complement subtraction. The system further includes a means for performing an exclusive OR operation using the carry out and a virtual bit associated with a highest rename buffer within the plurality of rename buffers to form a result. An additional means for performing an exclusive OR operation is provided to compare the result with a most significant bit of the target pointer. Finally, an indicating means is provided to indicate a match between the most significant bit of the target pointer and the result, and therefore whether an instruction can be issued.

Virtual register renamed instruction issue for execution upon virtual/physical rename buffer wrap around detection signaling available physical register

An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent &ldquo;pipes&rdquo; from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the &ldquo;fpr target&rdquo;) are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand. In this situation, the mechanism prioritizes the first of the two instructions to be issued to the pipe satisfying the dependency, while the second instruction is preempted in favor of issuing an independent instruction or an instruction whose dependent data has already been made available to the other pipe when such an instruction is waiting in a queue.

An FPSCR (Floating Point Status and Control Register) mechanism supports out-of-order floating point unit instruction execution. The FPSCR mechanism provides appropriate reporting of exceptions to a re-order buffer implemented within a data processing system to allow precise interrupts during out-of-order instruction execution. Additionally, the FPSCR mechanism allows for the retention of the appropriate status and control history information in an FPSCR rename buffer to allow the floating points status and control register to be maintained as though instructions were being executed in order. Additionally, the FPSCR mechanism generates the FPSCR's sticky exception status in concordance with reporting appropriate status to the previously mentioned re-order buffer and saving history into the FPSCR rename buffer. Furthermore, the FPSCR mechanism generates non-sticky status bits in addition to an FPU pipe state for retention in the FPSCR rename buffer in addition to an instruction issue mechanism that supports the generation of FPU pipe state bits to support calculation of non-sticky status bits stored within the FPSCR. By implementing each of these functions, the FPSCR mechanism permits the out-of-order execution of eligible floating point unit instructions.

Data processing system having an apparatus for tracking a status of an

An FPSCR (Floating Point Status and Control Register) mechanism supports de-serialized floating point unit (FPU) instruction execution. The FPSCR mechanism provides for speculative execution of all FPU instructions. In particular, instructions that directly alter FPSCR data values may be executed speculatively. Instructions of this type which may be de-serialized include the move-from FPSCR instruction, the move-to-condition register from FPSCR instruction, the move-to FPSCR field immediate instruction, the move-to FPSCR field instruction, the move-to FPSCR bit 0 instruction, the move-to FPSCR bit 1 instruction, as well as FPU register-to-register instructions having a recording bit set. Speculative execution is implemented by providing an accurate working FPSCR at the time the speculatively executing instruction sources FPSCR data. Moreover, the FPSCR mechanism re-establishes the working FPSCR when exceptions occur, or speculative execution is cancelled. The FPSCR de-serialization mechanism is compatible with prior art out-of-order FPU register-to-register instruction execution. By implementing each of these functions, the FPSCR mechanism permits the out-of-order execution of eligible floating point unit instructions.

Data processing system having an apparatus for de-serialized status

A method and system for interchanging operands and loading such operands into a plurality of operand registers in an execution unit with the data processing system during execution of a complex instruction. A plurality of operands are stored within a register file, including a first operand and a second operand. An instruction is loaded into the first stage of the execution pipe within the execution unit, wherein the instruction has a plurality of fields. Such fields include a first and second field, containing a first and second operand pointer, respectively, for designating a value stored in the register file for loading into first and second operand registers, respectively. Next, the first and second operand pointers are interchanged between the first and second fields. Finally, the first operand register is loaded with the value in the register file designated by the second operand pointer stored in the first field, and the second operand register is loaded with the value in the register file designated by the first operand pointer in the second field, wherein the values in the register file designated by operand pointers in the fields of the instruction are loaded into different operand registers than originally specified by the instruction, thereby facilitating execution of a complex instruction in the execution unit.

Method and system for interchanging operands during complex instruction

A method and apparatus for looking up source matches in a central processing unit (CPU) is utilized to identify dependencies between instructions that have been renamed via buffer renaming techniques. In such instances, when a particular instruction's source is a previous instruction's destination, that match needs to be identified such that dependent relationships between instructions are maintained. The source lookup method and apparatus utilize an allocation pointer and deallocation pointer, which point to the rename buffer, to produce a comparison window. For a given source of a given instruction, the comparison window is used to compare whether the source in question has a match within the rename buffer. If only one match is found, that rename buffer location is flagged to indicate that this particular location has a dependent relationship with the current source in question. If more than one match has been identified, a selection is made to choose the buffer location closest to the allocation pointer.

Method and apparatus for source lookup within a central processing unit

A selectable adder/hashing circuit generates a hashed virtual address from address operands within or derived from a program instruction. The hashed virtual address is used to address a translation lookaside buffer (TLB). The hashing function and addition function each comprise multiple steps. Some of the hashing function steps are performed in parallel with some of the steps of the addition function, and other of the hashing function steps are performed within other of the addition function steps. Therefore, the hashing function does not add delay over that required to produce an un-hashed virtual address from an addition function performed on the address operands. The hashing function can be enabled or disabled to meet the needs of the particular program environment. A method for generating the un-hashed address from the hashed address determines if the contents of the TLB location addressed by the hashed address match the unhashed virtual address. If so, the real address corresponding to the unhashed virtual address can be obtained from the TLB without requiring a time consuming address translation.

Growing community of inventors

Round Rock, TX, United States of America

James Edward Phillips