Other

Motorola Corporation

International Business Machines Corporation

James Edward Dunning

Peter Juergen Klim

James R Lundberg

Christopher McCall Durham

John Stephen Muhich

Marlin Wayne Frederick, Jr

John Beck

James G Gay

Richard S Ramus

False transitions resulting from capacitive coupling between parallel interconnects driven by dynamic circuits are reduced by classifying interconnects based on the timing of expected data transitions in the signals they carry. Interconnects carrying signals expected to transition during a first portion of a processor cycle are treated as one category, while interconnects carrying signals expected to transition during a second, different portion of the processors cycle are treated as a second category. Interconnects of different categories are interdigitated, a resets of dynamic driving circuits are tuned so that, at any given time, alternate interconnects are &ldquo;quiet&rdquo; or stable. Therefore interconnects being driven with data transitions are directly adjacent to quiet lines, and foot devices are implemented as necessary to prevent coupling expected during the reset phase. Such foot devices are implemented within receiving circuits to preclude capacitive coupling between the driven interconnect and the quiet line from having any significant effect. Extra quiet lines may be employed as needed. The evaluation phases of dynamic circuits driving adjacent interconnects may overlap, so that an interconnect within a first category is high or low&mdash;but not transitioning&mdash;when an adjacent interconnect within a second category is rising or falling, and vice versa. The evaluation phases may also be completely offset, so the an interconnect within a first category is low when an adajcent interconnect within the second category is rising, high, or falling.

Coupling noise reduction technique using reset timing

A domino logic circuit having output noise elimination is disclosed. A compound domino logic circuit includes at least two trees of logic devices arranged in parallel, with each tree having a precharge transistor connected to a power supply, and one or more input transistors coupled between the precharge transistor and ground. The precharge transistor receives a clock input while each of the one or more input transistors receives a signal input. The compound domino logic circuit also includes a logic gate coupled to the precharge transistor to produce a signal output. The logic gate includes at least two transistors connected in series. Further, an adjustment transistor is coupled to a node between the two transistors to ground.

Compound domino logic circuit having output noise elimination

An adder (300) generates encoded outputs to conserve power. In particular, the adder provides 'B2' encoded outputs which only drive one bit per every two bits at a time on conductive lines in a data processing system. A binary input is encoded by an encoder (800, 304) to generate a plurality of bits. The plurality of bits are concatenated to form a plurality of sum values. A portion of the plurality of sum values are then selectively output in response to a logic value of a carry kill signal, a carry generate signal, and a carry propagate signal.

Adder circuit and method therefor

An output driver circuit has a circuitry portion (70) which is used to generate a Drive-Hi control signal in response to an Output Enable, an optional Precondition signal, and a Data Input signal. A circuit portion (75) ensures that the Drive-Hi control signal is maintained at a voltage which is substantially equal to Vdd when the Output Enable is deactivated. Circuit portion (80) selectively controls the Data Output by driving Vdd onto the Data Output in response to the Drive-Hi control signal being activated. A circuit portion (100) functions to selectively drive the Data Output to a logic zero (ground potential) when a Drive-Lo signal is asserted. Circuit portions (90 and 95) generate the Drive-Lo signal in response to the Output Enable, the optional Precondition signal, and the Data Input signal. In general, the output driver circuit allows an integrated circuit powered at a first voltage to interface to another integrated circuit which is powered at a higher second voltage without loss of performance, without excessive leakage currents, without crossover current, and without increasing gate oxide stresses.

Output circuit for interfacing integrated circuits having different

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Austin, TX, United States of America

James Edward Dunning