National Semiconductor Corporation

Maxim Integrated Products, Inc.

Omni Design Technologies, Inc.

James Edward Bales

Denis Clarke Daly

Vikas Singh

An analog-to-digital conversion (ADC) system is operated with a duty cycle. During the ON period, the ADC circuits perform analog-to-digital conversions of an analog input signal. During the Standby period, the ADC system is in either a standby state or a foreground calibration state. The ADC system operates in a reduced-power mode in the standby state. In the foreground calibration state, the ADC system performs a portion of a foreground calibration cycle during a calibration time slot. The foreground calibration cycle is performed over multiple calibration time slots. The foreground calibration cycle and the calibration time slots are configurable by changing the values of control registers that represent calibration parameters.

Duty-cycled analog-to-digital converter system with programmable foreground calibration

A time-interleaved sampling system includes an input signal having a time-varying analog value and a plurality of samplers. Each sampler is operable in a hold mode and a track mode. In the track mode, the samplers track the analog value of the input signal. In the hold mode, each sampler holds a respective analog value of the input signal that a respective sampler tracked immediately before entering the hold mode. The samplers enter the track mode in a predetermined sequence. After a last sampler in the predetermined sequence enters the track mode, the predetermined sequence is repeated in a loop. At random intervals, a skipped sampler in the predetermined sequence is bypassed from entering the track mode.

Time-interleaved sampling circuits with randomized skipping

A pipeline analog-to-digital converter (ADC) includes a first conversion stage of the pipeline ADC that receives an input signal and that comprises, in a first signal path, a first ADC that converts the input signal, a first digital-to-analog converter (DAC) that converts an output of the first ADC, a first subtractor that subtracts an output of the first DAC from the input signal, and a first amplifier that amplifies an output of the first subtractor and generates a first residue of the first conversion stage; and in a second signal path, a second DAC that converts the output of the first ADC, a second subtractor that subtracts an output of the second DAC from the input signal, and a second amplifier that amplifies an output of the second subtractor and generates a second residue of the first conversion stage. A control module selectively enables and disables the second path.

Reconfigurable multiple-path pipeline ADC architecture incorporating multiple-input signal-averaging MDAC

A single operational transconductance pipelined ADC incorporating a sample/hold amplifier and multiple MDAC stages. An input signal is sampled on input signal sampling capacitors, and then coupled around an operational transconductance amplifier (OTA) so that the output of the OTA is equal to the sampled voltage. There is no net charge transfer in this operation, so the noise and power dissipation normally associated with an input sample and hold circuitry (SHA) in a pipelined ADC is substantially eliminated. A pipelined ADC using a shared OTA for sample/hold and two MDACs is disclosed.

Shared operational transconductance amplifier pipelined ADC incorporating a sample/hold amplifier and multiple MDAC stages

A system comprises a switched capacitor amplifier including an operational amplifier (opamp). A switching circuit comprises a first switch connected across inputs of the opamp. A second switch is connected across outputs of the opamp. An overdrive detect circuit communicates with the first and second switches and selectively shorts the inputs and the outputs of the opamp when the input voltage is greater than a first predetermined overdrive voltage or when the input voltage is less than a second predetermined overdrive voltage.

Switched capacitor amplifier circuit with clamping

A level translating circuit suitable for converting ECL level signals to CMOS level signals. The ECL signal is converted to a pair of buffered differential signals that are level shifted and divided to produce four transistor drive signal, two of which are connected to the respective gate and source of a P-type MOS transistor and two of which are connected to the respective gate and source of another P-type MOS transistor. An N-type transistor is connected in series with each of the P-type transistors so as to provide CMOS outputs at the junction of the N and P-type transistors.

Complementary MOS level translating apparatus and method

A complementary class AB current mirror circuit with a constant current gain which, when driven by a transconductance amplifier, provides a constant overall voltage gain over a wide range of output current. Such current mirror circuit includes cross-coupled pairs of current mirror circuits, both of which are driven by a common reference current and each of which selectively receives a respective portion of the input signal current. The upper pair of current mirror circuits includes: an input current mirror circuit which generates a drive current for the output stage of the lower pair of current mirror circuits; and an output current mirror circuit which generates the source, or 'push,' portion of the output signal current. The lower pair of current mirror circuits includes: an input current mirror circuit which generates a drive current for the output stage of the upper pair of current mirror circuits; and an output current mirror circuit which generates the sink, or 'pull,' portion of the output signal current.

Complementary class AB current amplifier

A complementary Class AB output stage including a Class AB complementary common emitter quiescently biased by means of current mirrors and a Class AB complementary emitter follower circuit having its emitters connected to the common emitter stage outputs and its collectors connected to the base terminals of the common emitter transistors thus achieving large output swing and large output drive current with very low quiescent current in the common emitter portion of the circuit.

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Fort Collins, CO, United States of America

James Edward Bales