Digital Equipment Corporation

James E Tessari

Michael A Gagliardo

John J Lynch

Kumar Chinnaswamy

Paul M Goodwin

Michael B Evans

Hansel A Collins

Timothy P Fissette

A method and apparatus for providing asynchronous communication between at least one central processing unit (CPU) and at least one associated memory unit with specially programmed timing signals to latch, select and transmit data between them.

Programmable data transfer timing

Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a system control unit (SCU) with special data transfer cycles. The special data transfer cycles include a first dual operation mode which confirms that the transferred data is the most current and then concurrently write the CPU transferred data into the SCU main memory while transferring it directly to the requesting CPU, and a second dual operation mode which confirms that only a portion of the transferred data is the most current and then concurrently write the portion of the transferred data that is most current in the SCU memory and read the written data for transfer to the requesting CPU.

Write-read/write-pass memory subsystem cycle

Methods and apparatus for immunizing dynamic random access memory (DRAM) modules in the data processing system against data loss from transitions that occur with memory mode switching during the scan operation and permitting normal operations to be performed on the memory modules regardless of the state of the system clocks.

Method and apparatus for performing diagnosis scanning of a memory unit

Mode switching for a memory system with diagnostic scan

A method and apparatus for a read-modify-write operation in a digital computer memory system that reduces memory data path buffer storage requirements. The method latches new write data and associated mask fields into a data output buffer and then uses the latched mask fields to merge read data with the new data in the output buffer. The mask fields determine which portion of the read data is to be replaced with new data. Appropriate check bits for an error correction code (ECC) are generated and added to the modified data in the output buffer to produce a new data output which is released from the output buffer into the memory at the selected address.

Method and apparatus for reducing buffer storage in a read-modify-write

Methods and apparatus for reducing memory read latency for selected data requested by one central processing unit (CPU) and retrieved from another CPU through a system control unit (SCU) with special data transfer cycles. The special data transfer cycles include a first dual operation mode which confirms that the transferred data is the most current and then concurrently writes the CPU transferred data into the SCU main memory while transferring it directly to the requesting CPU, and a second dual operation mode which confirms that only a portion of the transferred data is the most current and then concurrently writes the portion of the transferred data that is most current in the SCU memory and reads the written data that is most current in the SCU memory and reads the written data for transfer to the requesting CPU.

Method and apparatus for reducing memory read latency in a shared memory

In a multi-processing computer system including a plurality of central processing units (CPUs) and input/output (I/O) units, a system memory including a plurality of DRAM-based memory segments, a system control unit (SCU) for operating the CPUs in a parallel fashion and allowing the CPUs and other system units to controllably access addressable segments of system memory, and an interface for establishing communication between the SCU and the system memory and regulating the transfer of memory commands and associated data therebetween, the system memory is configured in the form of at least one independently accessible memory unit having a first dedicated data path for the transfer of read data from addressed memory segments to the interface for transfer to the SCU, a second dedicated data path for transfer of write data received from the SCU through the interface to addressed memory segments, and a third dedicated path for transfer of addresses from the SCU to identify addressed segment of memory.

Memory configuration for use with means for interfacing a system control

A method and apparatus for a read-modify-write operation in a digital computer memory system which reduces memory data path buffer storage requirements with a procedure which includes latching new write data and associated mask fields into a data output buffer and then merging read data with the new data in the output buffer according to the latched mask fields.

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Arlington, MA, United States of America

James E Tessari