International Business Machines Corporation

Globalfoundries Inc.

James E Sundquist

James Douglas Warnock

Sachin Gupta

Vasant B Rao

Suriya T Skariah

Peter Anton Habitz

Amith Singhee

Wangyang Zhang

Henry A Bonges, Iii

Amol Anil Joshi

David C Reynolds

An approach is provided in which an information handling system executes multiple timing constraint sensitivity tests on a circuit model using a first signal arrival time and generates multiple test results. The information handling system compares the multiple test results with a pre-determined probability threshold and, in response to determining that an amount of test failures included in the multiple test results meets a pre-determined failure probability threshold, the information handling system computes a timing constraint sensitivity of the circuit model based upon the first signal arrival time. The information handling system compares the timing constraint sensitivity against a characterized sensitivity generated by a software modeling system and, when the timing constraint sensitivity does not match the characterized sensitivity, one or more of the software modeling system's modeling parameters are adjusted, causing the software modeling system to generate a changed characterized sensitivity of the circuit model.

Validating variation of timing constraint measurements

A method is disclosed comprising using a circuit recognition engine running on a computerized device to detect a number and type of devices in an integrated circuit. The method characterizes device variation by selecting a set of dominant active devices and performing simulation using the set of dominant active devices. Three different options may be used to optimize the number of simulations for any arc/slew/load combination. Aggressive reduction uses a minimal number of simulations at the cost of some accuracy loss, conservative reduction reduces the number of simulations with negligible accuracy loss, and dynamic reduction dynamically determines the minimum number of simulations needed for a given accuracy requirement.

Dynamically determining number of simulations required for characterizing intra-circuit incongruent variations

A method of performing latch up check on an integrated circuit (IC) design that comprises rasterizing a conductor region shape and contact shapes and iteratively expanding the contact shapes within the conductor region shape using a cellular algorithm. Direction values for contact cells can be used to limit the number of neighboring cells which must be explored. In every fourth iteration of the expansion process, corner cells may not be expanded. Reachable areas outside of conductors can also be explored.

Method of performing latch up check on an integrated circuit design

Growing community of inventors

Colchester, VT, United States of America

James E Sundquist