Intel Corporation

James E Smith

Koichi Yamada

Sebastian Winkel

Suresh Srinivas

Youfeng Wu

Shiliang Hu

Denis M Khartikov

A system and method to enhance execution of architected instructions in a processor uses auxiliary code to optimize execution of base microcode. An execution context of the architected instructions may be profiled to detect potential optimizations, resulting in generation and storage of auxiliary microcode. When the architected instructions are decoded to base microcode for execution, the base microcode may be enhanced or modified using retrieved auxiliary code.

Modified execution using context sensitive auxiliary code

In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environment

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Missoula, MT, United States of America

James E Smith