Xilinx, Inc.

Unmanned Innovation, Inc.

Skydio, Inc.

James E Ogden

Bernard J Michini

Jonathan Downey

Donald Curry Weigel

Joseph Moster

Stacey Secatch

Michael George Ingoldby

James M Simkins

Subodh Kumar

Jeffrey C Ward

Uma E Durairajan

Matthew H Klein

Thomas E Fischaber

Thomas H Strader

Restu I Ismail

Mark R McLaughlin

Scott J Fischaber

Kumar Subodh

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for unmanned aerial vehicle authorization and geofence envelope determination. One of the methods includes determining, by an electronic system in an Unmanned Aerial Vehicle (UAV), an estimated fuel remaining in the UAV. An estimated fuel consumption of the UAV is determined. Estimated information associated with wind affecting the UAV is determined using information obtained from sensors included in the UAV. Estimated flights times remaining for a current path, and one or more alternative flight paths, are determined using the determined estimated fuel remaining, determined estimated fuel consumption, determined information associated wind, and information describing each flight path. In response to the electronic system determining that the estimated fuel remaining, after completion of the current flight path, would be below a first threshold, an alternative flight path is selected.

Unmanned aerial vehicle authorization and geofence envelope determination

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for unmanned aerial vehicle authorization and geofence envelope determination. One of the methods includes maintaining, in a datastore, flight operation information associated with UAV flight operations. A request to generate a risk assessment report is received, with the request including aspects of a UAV flight operation, with the risk assessment report describing risk associated with each aspect. Flight operation information accessed from the datastore is analyzed. Performance characteristics are determined based at least in part on the analysis of the flight operation information, with the performance characteristics including information that can inform, or affect, a safe or functional UAV flight operation. Risk assessments for each aspects in the request are determined using the performance characteristics. The risk assessment report is generated using the determined risk assessments.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for unmanned aerial vehicle authorization and geofence envelope determination. One of the methods includes maintaining, by a cloud system in wireless communication with Unmanned Aerial Vehicles (UAVs), allocated geofence envelopes for one or more of the UAVs, with each geofence envelope being a virtual barrier for a real-world geographic area. A request for approval of an updated geofence envelope is received from a first UAV in flight. The cloud system determines that the updated geofence envelope has not been allocated and/or the updated geofence envelope does not interfere with allocated geofence envelopes. In response to the determination, a response indicating approval of the request is generated. The generated response is provided to the first UAV.

An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.

Configurable embedded memory system

An integrated circuit and method for using a synchronous reset pulse to reset a circuitry comprising a plurality of clock domains are disclosed. For example, the method of the present disclosure provides a reset signal that is synched to one clock, takes the synchronous signal and resets circuits in a plurality of clock domains. In order to reset a portion of the circuit which is in a particular clock domain, the reset needs to be synchronized to the clock of the particular domain.

Method and apparatus for using a synchronous reset pulse to reset circuitry in multiple clock domains

Methods of generating a PLD design implementation according to a design architecture tailored to specified requirements. A hardware description language (HDL) description for the PLD design includes at least one parameter value for the PLD design that will affect the preferred implementation of the design. This parameter value is passed to a high-level language (HLL) function, which is used to determine a tailored design architecture in accordance with the specified needs of the target application. The HLL function returns data specifying the tailored design architecture. This data is used in generating an implementation of the PLD design that follows the constraints imposed by the tailored design architecture. The result can be, for example, a logic gate representation of the PLD design, a netlist of the design, or a bitstream implementing the design in a target PLD.

Methods of generating a design architecture tailored to specified requirements of a PLD design

A method of integrating a High-level Language (HLL) function with a Hardware Description Language (HDL) representation of a circuit design can include identifying an attribute of the HDL representation of the circuit design that is resolved at compile time and determining a value for the attribute using an HLL function when compiling the HDL representation of the circuit design.

Using high-level language functions in HDL synthesis tools

Memory circuits that concatenate multiple FIFOs in parallel to increase the overall depth of the memory circuits. Asymmetric input and output ports can be provided by including a deserializer on the write interface of the memory circuit and/or a serializer on the read interface of the memory circuit. The deserializer disperses the data evenly across all FIFOs, minimizing the write-to-read latency. In some embodiments, at most two of the FIFOs are active at any given time, one being written and one being read, which reduces the overall power consumption of the memory circuit compared to known structures.

Circuits providing greater depth and/or asymmetric access ports for first-in first-out memory circuits (FIFOs)

Computer-implemented methods of mapping a logical representation of a memory to physical memory, e.g., in a programmable logic device (PLD). The logical representation of the memory is input into the computer, which generates an initial solution (e.g., a column-based solution) for the memory. In a column-based solution, the primitives are arranged such that each column includes only one type of primitive. The column-based solution generated in this step uses the minimum number of primitives attainable by a column-based approach. The column-based solution is then modified to reduce multiplexing, e.g., by replacing two primitives that are cascaded in depth with two primitives that are cascaded in width. In some embodiments, the total number of primitives can be reduced by the modification. The resulting physical representation of the memory is then output, and can be utilized, if desired, to create an implementation of the memory targeted to a PLD.

Methods of mapping a logical memory representation to physical memory in a programmable logic device

Circuits and methods of rearranging the order of data in a memory having asymmetric input and output ports are disclosed. According to one embodiment, a method comprises steps of providing an input port of a memory having an input width and output port having an output width which is different than the input width. A plurality of data words are received at the input of the memory, wherein each data word has a width corresponding to the input width. The order of the plurality of input data words is rearranged; and an output word based upon the rearranged data words and having a width corresponding to the output width is generated. Various circuits and algorithms for implementing the methods are also disclosed.

Memory of and circuit for rearranging the order of data in a memory having asymmetric input and output ports

Apparatuses for binary priority encoding are described. A binary priority encoder (L) includes a data input bus (), a first logic tree () coupled to receive data from the input bus (), and a second logic tree () coupled to receive a portion of the data from the input bus (). The first logic tree () is configured to provide a flag signal () indicating whether at least one bit of the data is active. The first logic tree () is configured to provide control signals. The second logic tree () is coupled to receive the control signals. The second logic tree () is configured to select first partial addresses from the portion of the data responsive to the control signals. The control signals are further provided to the second logic tree () as second partial addresses.

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San Jose, CA, United States of America

James E Ogden