Texas Instruments Corporation

James E Nave

Haydar Bilhan

Eric G Soenen

Erkan Bilhan

Kirk D Peterson

Sucheendran Sridharan

Feng Ying

Jason Meiners

Todd Christopher Hiers

Bharadwaj Parthasarathy

Andrew J Cringean

Xiaodong Wu

James R Craig

Hyunkeun Kim

This invention is a video line encapsulation protocol which allows multiple low definition video streams to be combined into a single super frame of high definition video data. Each super frame is formed of individual lines from plural lower definition video input signals. The high definition video frames include meta data in each line identifying the video input source, line and frame. This meta data enables the super frames to be separated into their component input signals within a video processing digital signal processor.

Multichannel video port interface using no external memory

A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information.

Shared-PLL audio clock recovery in multimedia interfaces

A method for protecting secret keys, such as HDCP device key sets, during the manufacturing process is disclosed. In particular, the present invention comprises a method for securely sending and receiving data, such as HDCP device key sets, for use in a cryptosystem. In operation, a first party, referred to as a sender () is to send original data () to a second party, referred to as a recipient (). To facilitate the secure transmission, the recipient () randomly generates () a session key () and encrypts it with its private key-encryption key (). The recipient then securely sends both the encrypted and unencrypted session keys to the sender. The sender () then encrypts the original data () using the unencrypted session key () and includes the encrypted data () along with the encrypted session key () to the recipient (). The recipient () then decrypts the encrypted session key () using the private key-encryption key () and then decrypts the original data ().

Recipient-encrypted session key cryptography

A video decoder () for receiving an input video signal and producing output signals for a digital display (), and involving automatic gain control (AGC) functions (), is disclosed. For each of the front-end and back-end AGC functions (), the AGC gain value applied is modified according to measurements of several attributes of the video signal, such as sync height, color burst amplitude, composite signal peak amplitude, and luma signal peak amplitude. The measurements are made, and the AGC gains are modified, on a frame-by-frame basis. Preferably, the AGC is modified using the one of the signal attributes that indicates the lowest gain. The back-end AGC function () modifies its gain to unity if the front-end AGC function () selected the luma signal peak amplitude for modifying its gain. A method for adjusting the rate of change of the AGC gain is also disclosed, in which gain increases are delayed and slowed following an AGC gain decrease because of an image-dependent signal attribute.

Automatic gain control based on multiple input references in a video decoder

Disclosed are methods and systems for automatic level control (ALC) in a video signal processing system. The new ALC of the invention takes into account the gain applied to the video signal, such as that provided by an associated automatic gain control (AGC). Methods and systems of the invention use present gain control values and previous gain control values in quickly converging to a new offset control value.

Automatic level control (ALC) for video signals

Disclosed are methods and systems for automatic gain control (AGC) in circuits. The disclosed methods and systems provide accurate and rapidly converging automatic gain control suited for video applications. According to disclosed preferred embodiments of the invention, a signal amplitude controlling method is responsive to gain underflow or overflow. A new fine gain control value is extrapolated and a new coarse gain control value is determined. The new fine gain and new coarse gain control values are applied to the signal to produce an output signal within a pre-selected output amplitude range.

Fast-convergence two-stage automatic gain control (AGC)

An apparatus, system and method for clamping a video signal input to a coupling capacitor () for providing a clamping voltage. A charging current is applied to the capacitor () via an amplifier () having a first input () coupled with the capacitor output and a second input () coupled to a reference potential, the amplifier () is responsive to the capacitor output signal and the reference potential for providing the charging current to the capacitor (). The current has a linearly varying magnitude which is proportional to a difference between the capacitor output and the reference potential.

Clamping circuit for video signals

An integrated analog to digital interface subsystem for imaging applications includes digital global and digital pixel by pixel offset correction and scaling. The integrated interface 2 includes 3 DAC's 2c1-2c3 that are used to do a rough offset cancellation on the three analog input signals (RGB) in the analog domain. A triple sample/hold circuit 2a samples the RGB signals simultaneously, multiplexes the data and passes the three signals on the ADC 2b sequentially (at about 3 times the data rate). The sample/hold circuit 2a has the capability to operate in fully differential as well as single ended input mode, and can perform correlated double sampling if needed. A high resolution ADC 2b converts the 3 multiplexed signals from simple/hold circuit 2a. A first digital offset correction circuit 2f restores the level of the RGB signals in the digital domain on a pixel by pixel basis. A first digital gain correction circuit 2g compensates for sensitivity variations of the RGB sensors in the digital domain on a pixel by pixel basis. A second digital offset correction circuit 2h restores the overall DC level of the RGB signals in the digital domain. A second digital gain correction circuit 2i compensates for overall sensitivity variations of the RGB sensors in the digital domain. A serial interface 2d is used to load the overall gain and offset coefficients.

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Denton, TX, United States of America

James E Nave