Chips and Technologies, Llc.

Nvidia Corporation

3dfx Interactive, Inc.

Other

James E Margeson, Iii

Scott D Sellers

Gary Tarolli

Ignatius B Tjandrasuwita

James M Van Dyke

John Stephen Montrym

Emmett Michael Kilgariff

Douglas A Voorhies

Murali Sundaresan

Dane Mrazek

A computer graphics system provides for processing image data including Z data for use in displaying three-dimensional images on a display unit. The system includes: a depth buffer providing for temporary storage of Z data; and a graphics processing unit having a graphics engine for generating image data including Z data, and a memory interface unit communicatively coupled to the graphics engine and communicatively coupled to the depth buffer via a depth buffer interface. The graphics processing unit is operative to compress at least a portion of the generated Z data, to write the compressed portion of Z data to the depth buffer via the depth buffer interface in a compressed format, to read portions of compressed Z data from the depth buffer via the depth buffer interface, and to decompress the compressed Z data read from the buffer. An advantage of the present invention is that effective Z data bandwidth through the depth buffer interface is maximized in order to facilitate fast depth buffer access operations.

Method and apparatus for managing and accessing depth data in a computer graphics system

A system, method and computer program product are provided for texture sampling in a graphics pipeline. Initially, texture information is retrieved using texture coordinates. Thereafter, the texture information is utilized to generate results. Next, the texture information and the results are utilized to generate further results. The foregoing operation may optionally be repeated, and the results outputted.

System, method and computer program product for texture address operations based on computations involving other textures

A system, method and article of manufacture are afforded for providing an interlock module in a graphics pipeline. initially, first information is received indicative of a first set of pixels that overlap a primitive. Such first set of pixels are currently being processed in the graphics pipeline. Also received is second information indicative of a second set of pixels that overlap the primitive. The second set of pixels are ready for being inputted in the graphics pipeline for processing. Thereafter, the first information and the second information are evaluated, and the second set of pixels is conditionally processed based on the evaluation.

System, method and article of manufacture for an interlock module in a computer graphics processing pipeline

Data stream converter with increased grey levels

A texture compositing apparatus and method for combining multiple independent texture colors in a variety of ways in a single execution pass using a single texture compositing unit (TCU) per texture. The TCU receives a control signal, a blend factor, a local data signal(C.sub.local /A.sub.local) and an output data signal (C.sub.in /A.sub.in) generated by another TCU, the local data signal and the output data signal represent a texture color in a RGBA format. Based upon the control signal, the TCU can generate an output signal based on a variety of functions. The outputs that can be generated include but are not limited to: (1) zero; (2) one; (3) C.sub.in ; (4) C.sub.local ; (5) C.sub.in +C.sub.local ; (6) C.sub.in -C.sub.local ; (7) C.sub.in *C.sub.local ; (8) C.sub.in *C.sub.local +A.sub.local ; (9) C.sub.in *A.sub.local +C.sub.local ; (10) (C.sub.in -C.sub.local)* F.sub.blend +C.sub.local ; and (11) (C.sub.in -C.sub.local)*(1-F.sub.blend)+C.sub.local. Another feature of the invention is that multiple TCUs can be serially coupled to enable additional texture colors to be combined in a single execution path.

Texture compositing apparatus and method

A high quality texture filtering technique in a computer hardware system. The texture filtering quality of the present invention is comparable to trilinear filtering. However, the present invention reduces the number of memory accesses by fifty percent in comparison to trilinear filtering. To achieve this result, the present invention determines a pixel value based upon one or more texel values, e.g., four texel values, from only one of two mipmap levels. The mipmap level that is used is based upon the fractional portion of the LOD value and the position of the pixel. For a group of pixels having the same LOD value, the present invention performs a dithering operation that results in some pixel values being determined using texel values from the lower level mipmap and the remaining pixel values being determined using texel values from the higher level mipmap. The percentage of pixel values that are determined using texel values from the higher level mipmap is proportional to the fractional portion of the LOD value.

Level of detail texture filtering with dithering and mipmaps

A system and method for compressing and decompressing a texture image that: (1) compresses each texel to 8 bits, and when decompressed, each texel is of a quality comparable to a 256 color palettized image; (2) increases the efficiency of the decompression system and method by eliminating complex operations, e.g., multiplication; and (3) increases the efficiency of the system and method when switching between textures that use different palettes, when compared to conventional system and methods. The invention compresses a texture image, stores the compressed texture image, and quickly and efficiently decompresses the texture image when determining a value of a pixel. The texture image compression technique utilizes a palletized color space that more closely matches the colors in the texture image while allocating an unequal number of bits to the color channels. Each texel in the texture image is converted to an 8-bit value in the selected color space, and a decompression table is generated that represents the RGB values for the each texel stored in the selected color space. In order to map the texture image to the object, one or more texels that are associated with each pixel are decompressed. The present invention quickly and efficiently decompresses each texel using a hardware decompression unit. The decompression unit does not perform any multiplication operations.

System and method for narrow channel compression

A texture compositing apparatus and method for combining multiple independent texture colors in a variety of ways in a single execution pass using a single texture compositing unit (TCU) per texture. The TCU receives a control signal, a blend factor, a local data signal(C.sub.local /A.sub.local), and an output data signal (C.sub.in /A.sub.in) generated by another TCU, the local data signal and the output data signal represent a texture color in a RGBA format. Based upon the control signal, the TCU can generate an output signal based on a variety of functions. The outputs that can be generated include but are not limited to: (1) zero; (2) one; (3) C.sub.in ; (4) C.sub.local ; (5) C.sub.in +C.sub.local ; (6) C.sub.in -C.sub.local ; (7) C.sub.in *C.sub.local ; (8) C.sub.in *C.sub.local +A.sub.local ; (9) C.sub.in *A.sub.local +C.sub.local ; (10) (C.sub.in -C.sub.local)*F.sub.blend +C.sub.local ; and (11) (C.sub.in -C.sub.local)*(1-F.sub.blend)+C.sub.local. Another feature of the invention is that multiple TCUs can be serially coupled to enable addition texture colors to be combined in a single execution path.

A system is provided that allows for the synchronous operation of a memory controller within a computer when the local bus clock has become inactive for a predetermined period of time. The system includes a circuit that senses the presence of the local bus clock and dependent upon whether the local bus clock is active or inactive causes a switching circuit to switch to a second clock signal that is independent of the local bus clock to run the memory controller. In one embodiment, a pixel clock signal is utilized to run the memory controller when the local bus clock signal is not active.

System for allowing synchronous sleep mode operation within a computer

A memory controller is provided in which the address path is disabled by a sequencer to reduce power consumption when the sequencer is in an IDLE mode. When access is requested by the bus, the sequencer changes into an ALERT mode, thereby enabling the address path. Subsequently the sequencer then changes into an EXECUTE mode to perform data transfer operations. After the transfer is completed, the sequencer returns to the ALERT mode and an inactive time counter begins counting. If no access is requested before the counter reaches a predetermined number of counts, the sequencer returns to the IDLE mode and the address path is disabled to save power. However, if another cycle request occurs while in the ALERT mode, the EXECUTE mode is entered into immediately.

Power saving system for a memory controller

A frame buffer architecture for a graphics controller provides for conversion of cathode ray tube (CRT) data streams to multi-segment data streams. The buffer architecture operates such that the CRT frame rate is the same as the multi-segment frame rate. In so doing, a graphics controller can operate within its intended specification while operating at the same clock frequency whether in CRT or multi-segment mode. In addition, this architecture overcomes the other problems associated with prior art graphics controllers.

Frame buffer with matched frame rate

The present invention relates to An apparatus for converting cathode ray tube (CRT) to a dual panel data stream to be utilized. The present invention includes a frame buffer system for displaying data on a dual panel display, which comprises an upper and lower panel. The frame buffer system receives CRT data and displays panel refresh data in which one CRT frame generates one panel refresh frame. Through the use of this system, An increased number of gray level patterns can be provided, thereby increasing image resolution and quality.

Growing community of inventors

Santa Clara, CA, United States of America

James E Margeson, Iii