Ncr Corporation

Celerity Computing

James E Kocol

David B Schuck

Robert O Gunderson

Patricia Shanahan

Nicholas E Aneshansley

Andrew Jackson McCrocklin

Gary L Riddle

Daniel J Marro

Jeffrey P Anderson

James J Whelan

A direct-execution microprogrammable microprocessor system uses an emulatory microprogrammable microprocessor for direct execution of microinstructions in main memory through a microinstruction port. A microinstruction cache with a microinstruction address extension unit serving to communicate microinstructions from the main memory to the microprogrammable microprocessor. Virtual main memory accesses occur through a system multiplexer. A virtual address extension unit and a virtual address bus provide extension and redefinition of the main memory address space of the microprogrammable microprocessor. The system also uses a context switching stack cache and an expanded address translation cache with the microprogrammable microprocessor having a reduced and redefined microinstruction set with a variable microinstruction cycle.

Direct-execution microprogrammable microprocessor system

A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus includes a star coupler, first and second external transmission lines connecting each station to the star coupler, and first and second internal transmission lines within each station that are coupled to the first and second external transmission lines. The subsystems within each station are each coupled to the first and second internal transmission lines by a system bus interface. The system bus interface monitors the system bus for an idle condition, and passes a message from its subsystem to the system bus only when it detects an idle condition on the system bus. Each message on the system bus includes a postamble that is garbled by any system bus interface that detects an error in any message on the system bus. Each subsystem has a local memory that includes a mailbox for storing header information of messages that are to be copied by that subsystem. DMA circuitry in each system bus interface manages the operation of the mailbox in its subsystem. In alternate embodiments, the star coupler may be a magnetic star coupler or an electrical star coupler, and the system bus may be comprised of two channels, each channel including a star coupler and pairs of transmission lines connecting each station to the star coupler.

Data processing system wherein all subsystems check for message errors

Data processing system having dual-channel system bus

Data processing system wherein at least one subsystem has a local memory

A self-correcting memory system includes internal error detection and correction circuitry that periodically accesses each data word and a group of ECC check bits associated with each data word stored in the memory system. The error detection and correction circuitry includes an ECC checking circuit that receives the accessed data word, generates ECC bits, and compares those ECC bits to the group of ECC check bits associated with the data word. The resulting signal is used to correct any single bit in error, and to indicate the presence of a double bit error. A self-correct address counter is cascaded to a refresh address counter in the control circuitry of the memory system so that the accessing of each data word occurs during a refresh cycle of the memory system.

Self-correcting memory system

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Escondido, CA, United States of America

James E Kocol