Intel Corporation

James E Jaussi

Debendra Das Sharma

Bryan K Casper

Stephen R Mooney

Aaron K Martin

Mozhgan Mansuri

Joseph T Kennedy

Howard L Heck

Ganesh Balamurugan

Matthew B Haycock

Frank Patrick O'Mahony

Shekhar Yeshwant Borkar

David Stewart Dunning

David J Harriman

Mahesh U Wagh

Robert E Gough

Frank T Hady

Sergey Yuryevich Shumarayev

Sujit Sharan

Debendra Mallik

Tanay Karnik

Kristof Darmawikarta

Rahul N Manepalli

Ravindranath Vithal Mahajan

Nitin A Deshpande

Venkatraman Iyer

Christopher P Mozak

Zhichao Zhang

Zuoguo Wu

Debabani Choudhury

Su Wei Lim

Gang Duan

Joshua B Fryman

Daniel S Froelich

David J Comer

Chintan S Thakkar

Randy R Mooney

Bruce E Pederson

Gokce Keskin

Tawfiq Musah

Dave Dunning

Kenneth Brown

Shreyas Sen

Timothy Hollis

Rajesh Inti

Ling Liao

Xiaoqian Li

Andrew Alduino

Bai Nie

Jason M Gamba

Sameer Paital

Arnab Sarkar

Roger K Cheng

Tzu-Chien Hsueh

Harishankar Sridharan

Timothy M Wilson

Khaled Ahmed

Divya Pratap

Suresh V Pothukuchi

Kemal Aygün

Hariprasath Venkatram

Stefan Shopov

Hsien-Pao Yang

Bharadwaj Parthasarathy

Cooper S Levy

Sriram Venkataraman

Shiva Kiran

Pavan Kumar Kappagantula

Mohammed G Mostofa

Tanay Karnick

Ganesh Balamuragan

Bryan K Caspar

Thomas Liljeberg

Susheel Jadhav

Randy Mooney

Akshay Pethe

Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

High bandwidth optical interconnection architectures

An apparatus comprising a chip comprising a plurality of micro-emitters, the micro-emitters to couple to a plurality of data lines and to an optical fiber, wherein the micro-emitters are to generate optical signals for parallel transmission through the optical fiber, the optical signals corresponding to data communicated on the data lines.

Pseudo-monolithic data communication system

Embodiments may relate to a microelectronic package that includes a package substrate with an active bridge positioned therein. An active die may be coupled with the package substrate, and communicatively coupled with the active bridge. A photonic integrated circuit (PIC) may also be coupled with the package substrate and communicatively coupled with the active bridge. Other embodiments may be described or claimed.

Active bridge enabled co-packaged photonic transceiver

Embodiments disclosed herein include waveguides. In an embodiment, a waveguide comprises a conductive shell and a first ridge within the conductive shell. In an embodiment, the first ridge extends away from the conductive shell. In an embodiment, the waveguide further comprises a first core over the first ridge, where the first core comprises a first dielectric material with a first permittivity. In an embodiment, the waveguide may further comprise a second core embedded in the first core, where the second core comprises a second dielectric material with a second permittivity that is greater than the first permittivity.

Waveguides including at least one ridge associated with at least one dielectric core and the waveguides are surrounded by a conductive shell

A digital transmitter architecture is disclosed to transmit (TX) multi-gigabit per second data signals on single carriers (SC) or orthogonal frequency division multiplexing (OFDM) carriers at millimeter wave frequencies in either one of a high-resolution modulation mode or a spectral shaping mode. The architecture includes a number of digital power amplifier (DPA) and modulation reconfigurable circuit segments to process individual bits of a data bit stream in parallel according to a specific circuit configuration corresponding to the selected TX mode using a multiplexer to switch between configurations.

Ultra-high data rate digital mm-wave transmitter with energy efficient spectral filtering

Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Systems, methods, and apparatuses for stacked memory

An apparatus is provided which comprises: a first power supply rail to provide a first power supply; second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies; a first driver circuitry coupled to the first power supply rail and the second power supply rail; a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.

Dual power I/O transmitter

Some embodiments include apparatus and methods using an input node, an analog to digital converter (ADC) including an input coupled to the input node, a first feedforward equalizer (FFE) including an input coupled to an output of the ADC, a second FFE including an input coupled to the output of the ADC, and a decision feedback equalizer (DFE) including a first input, a second input, and an output, the first input coupled to an output of the first FFE, and the second input coupled to an output of the second FFE.

M-ary pulse amplitude modulation digital equalizer

Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits.

Interchangeable power and signal contacts for IO connectors

Embodiments of the present disclosure provide apparatuses and systems for proximity communications. The apparatus may include an integrated circuit (IC) package with a central processing unit (CPU) circuit, an input-output (I/O) circuit coupled with the CPU circuit, and a dielectric electromagnetic waveguide coupled with the I/O circuit, to enable communications between the CPU circuit and another apparatus. In another instance, the apparatus may include a plurality of coupler pads disposed on a first surface of the apparatus; and a processor electrically coupled with the coupler pads. One of the coupler pads may form capacitive coupling with one of coupler pads disposed on a second surface of another apparatus, in response to a placement of the first surface in at least partial contact with the second surface, to enable proximity data communication between the processor and the other apparatus. Other embodiments may be described and/or claimed.

Techniques for device-to-device communications

Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output.

Host controlled IO power management

Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The substrate may include a first side, a second side and a connection edge. The integrated buffer can be coupled to at least one of the first side and the second side of the substrate. A plurality of rows of contacts may be coupled to the first side of the substrate. Each row of contacts can be stacked substantially parallel to the connection edge. The substrate may have power outputs coupled thereto and the integrated buffer can include a voltage regulator that has a supply output coupled to the power outputs.

Rate scalable connector for high bandwidth consumer applications

Growing community of inventors

Hillsboro, OR, United States of America

James E Jaussi