Compaq Computer Corporation, Inc.

Digital Equipment Corporation

Cambridge Mobile Telematics Inc.

Hewlett-packard Development Company, L.p.

Compaq Information Technologies Group, L.p.

James E Hicks, Jr

Jeffrey Adgate Dean

William Edward Weihl

Carl Alan Waldspurger

George Z Chrysos

Hari Balakrishnan

Edward J McLellan

Daniel Lawrence Leibholz

Samuel Ross Madden

Lewis David Girod

Ben Bowne

Katherine Wellman

Joel S Emer

Tryggve Fossum

Bruce Edwards

Robert A Eustace

Matthew H Reilly

Jennifer-Ann M Anderson

Craig B Zilles

Christopher F Joerg

Rebecca L Stamm

Andrew Dean Christian

Steven M Ayer

Stephen C Root

Donald R Denning, Jr

Frank C Bomba

Personal safety concerns for users of vehicles can be indicated, identified, communicated, analyzed, or acted on to make the users and other participants in the technology aware of the safety concerns and to reduce the risks to the users associated with the safety concerns. Personal safety concerns can be recognized based on safety concern triggers. Once recognized, the personal safety concerns can be reported to the users and other participants in the technology by safety alerts. The safety alert can prompt one or more telematics devices at the vehicle to capture, store, or transmit telematics data, including, for example, audio, image, or video data or combinations of them. The captured telematics data can be used to verify the safety alert and the safety concern and present the captured data to a third party participant to enable the third party participant to determine an appropriate response or action.

Safety for vehicle users

A method and apparatus keeps track of ingestible objects (such as pills or food items) ingested by humans or animals. The objects are supplied with radio frequency identification (RFID) tags encoding data describing the objects. The humans or animals ingesting the objects are equipped with RFID sensors for detecting, decoding, and archiving the data encoded in the tags. A user may scan the body of the human or animal subject with a sensor to determine if a tagged object has been ingested. The tags may be covered with substances or contain elements that dissolve upon entering a digestive system. This allows detection of ingestion and also allows the RFID tag encoding to change in the course of digestion.

Method and apparatus for verification of ingestion

Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.

Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers

A method is provided for scheduling execution of a plurality of threads executed in a multithreaded processor. Resource utilizations of each of the plurality of threads are measured while the plurality of threads are concurrently executing in the multithreaded processor. Each of the plurality of threads is scheduled according to the measured resource utilizations using a thread scheduler.

Method for scheduling threads in a multithreaded processor

Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit

A method for sampling the performance of a computer system is provided. The computer system includes a plurality of functional units. The method selects transactions to be processed by a particular functional unit of the computer system. State information is stored while the selected transactions are processed by the functional unit. The state information is analyzed to guide optimization.

Apparatus and method for monitoring a computer system to guide optimization

A method estimates statistics of properties of transactions processed by a memory sub-system of a computer system. The method randomly selects memory transactions processed by the memory sub-system. States of the system are recorded as samples while the selected transaction are processed by the memory sub-system. The recorded states from a subset of the selected transactions are statistically analyzed to estimate statistics of the memory transactions.

Method for estimating statistics of properties of memory system transactions

A method is provided for guiding virtual-to-physical mapping policies in a computer system including a processor and a memory. State information is randomly sampled from selected memory references in a stream of memory references issued by the processor to the memory. Cache hit/miss status, translation-look-aside buffer hit/miss status, and effective virtual and physical memory addresses of the sampled memory references are recorded in a profile record. The recorded information is aggregated by virtual memory address, and a new virtual-to-physical mapping is choosen to reduce cache and translation-look-aside buffer miss rates.

Method for providing virtual memory to physical memory page mapping in a computer operating system that randomly samples state information

An apparatus for sampling states of a computer system having a hierarchical memory arranged at a plurality of levels, the hierarchical memory storing data at addresses. The apparatus includes a selector for selecting memory transactions based on first state and transaction information. The memory transactions are to be processed by the hierarchical memory. A trigger activates the selector based on second state and transaction information. A sampler stores states of the computer system that are identified with the selected instructions while processing the selected memory transactions in the hierarchical memory.

Apparatus for spatial and temporal sampling in a computer memory system

An apparatus is provided for sampling instructions in a processor pipeline of a computer system. The pipeline has a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A subset of the fetched instructions are identified as selected instructions. Event, latency, and state information of the system is sampled while any of the selected instructions are in any stage of the pipeline. Software is informed whenever any of the selected instructions leaves the pipeline to read the event and latency information.

Apparatus for sampling instruction execution information in a processor pipeline

An apparatus is provided for determining an average number of instructions entering a stage of a processor pipeline of a computer system during a clock cycle of a processor clock. The number of instructions entering a particular stage of the pipeline are stored in a queue during each of a predetermined number (N) of clock cycles. The total number of instructions processed over the last P clock cycles is computed, where P is less than or equal to N. The total number of instructions processed is divided by the last P processor cycles to yield the instantaneous average number of instructions processed for each processor cycle. This average number of instructions processed is communicated to software.

Apparatus for determining the instantaneous average number of instructions processed

An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A subset of the the multiple selected instructions to execute concurrently in the pipeline. State information of the system is sampled while any of the multiple selected instructions are in any stage of the pipeline. Software is informed whenever all of the selected instructions leave the pipeline so that the software can read any of the state information.

Method and apparatus for sampling multiple potentially concurrent

An apparatus is provided for collecting state information associated with an execution path of recently processed instructions in a processor pipeline of a computer system. The apparatus identifies a class of instructions to be sampled. Path-identifying state information of a currently processed instruction is sampled when the currently processed instruction belongs to the identified class of instructions. A shift register stores a predetermined number of entries storing selected state information, the shift register is simultaneously sampled along with additional state information about the instruction being executed at the time of sampling.

Growing community of inventors

Newton, MA, United States of America

James E Hicks, Jr