Micron Technology Incorporated

Other

James E Green

Darwin A Clampitt

Hasan Nejad

Philip J Ireland

Mark Fischer

Terrence B McDaniel

Terry McDaniel

Rita J Klein

Dale Collins

Justin R Arrington

Michael D Kenney

Nicholas E Paulin

A structural joint system connects hollow structural members that provide load transfer and alignment for the connection between structural members is described. The structural members may comprise a plurality of beams each having a first and second structural members. A first and second members being joined may or may not be axially aligned. In some embodiments, the structural joint includes a first structural member having a first mating face at one end of the first structural member, the first mating face having a two dimensional profile, a second structural member having a second mating face at one end of the second structural member and positioned proximate to the first mating face of the first structural member, the second mating face having a two dimensional profile that is similar to the two dimensional profile of the first mating face, a splice plate secured to the first structural member at the first mating face and removably secured to the second structural member at the second mating face, and fasteners that secure the splice plate to the first structural member and removably attach the splice plate to the second structural member.

Self-supporting and load bearing structural joint

In some embodiments, the structural joint includes a first structural member having a first mating face at one end of the first structural member, the first mating face having a two dimensional profile, a second structural member having a second mating face at one end of the second structural member and positioned proximate to the first mating face of the first structural member, the second mating face having a two dimensional profile that is similar to the two dimensional profile of the first mating face, a splice plate secured to the first structural member at the first mating face and removably secured to the second structural member at the second mating face, and fasteners that secure the splice plate to the first structural member and removably attach the splice plate to the second structural member.

Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate regions of the memory device. As the size of semiconductor components decreases and circuit densities increase, the density of the metal routing in these upper metal layers becomes increasingly difficult to fabricate. By providing additional metal routing in the lower gate regions that may be coupled to the upper metal layers, the spacing requirements of the upper metal layers may be eased, while maintaining the size of the semiconductor device. In addition, the additional metal routing formed in the gate regions of the memory devices may be disposed parallel to other metal contacts in a strapping configuration, thus reducing a resistance of the metal contacts, such as buried digit lines of a DRAM memory cell.

Additional metal routing in semiconductor devices

The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Method of fabricating integrated circuitry

A transportable, modular, self-contained shipping container building which has an optional means to collect, store, and distribute power from natural resources and a means to collect store, distribute and/or purify potable and/or non-potable water.

Transportable, modular, self contained shipping container building

A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.

Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same

A high surface area capacitor structure includes a storage electrode with recesses. An upper surface of the storage electrode has a maze-like appearance. Low elevation regions of a hemispherical grain polysilicon layer may remain on the upper surface of the storage electrode. The storage electrode or portions thereof may be lined or coated with dielectric material. The dielectric material may space a cell electrode of the high surface area capacitor structure apart from the storage electrode. One or both of the storage electrode and the cell electrode may be formed from polysilicon. Intermediate structures, which include mask material over contiguous low elevation regions of a layer of hemispherical grain polysilicon, which may have a maze-like appearance, and apertures located laterally between the low elevation regions of the layer of hemispherical grain polysilicon, are also disclosed.

High surface area capacitor structures and precursors

The invention includes methods of forming pluralities of electrically conductive structures. The methods can include formation of a gradient-containing material across a substrate and in direct physical contact with conductive surfaces of nodes. The gradient-containing material can consist essentially of tantalum nitride at a lowermost portion in contact with the conductive surfaces, consist essentially of tantalum at an uppermost portion, and have a TaN/Ta gradient extending between the lowermost and uppermost portions. Alternatively, the gradient-containing material can have a Co/W gradient extending therethrough. Conductive structures can be formed over the gradient-containing material. The invention also includes constructions comprising electrically conductive lines over a material having a TaN/Ta gradient, or a W/Co gradient, extending therethrough.

Methods of forming conductive structures

A honeycomb/webbed, high surface area capacitor formed by etching a storage poly using an etch mask having a plurality of micro vias. The etch mask is preferably formed by applying an HSG polysilicon layer on a surface of the storage poly with a mask layer being deposited over the HSG polysilicon layer. An upper portion of the mask layer is removed to expose the uppermost portions of the HSG polysilicon layer and the exposed HSG polysilicon layer portions are then etched, which translates the pattern of the exposed HSG polysilicon layer portions into the storage poly. The capacitor is completed by depositing a dielectric material layer over the storage poly layer and depositing a cell poly layer over the dielectric material layer.

High surface area capacitors and intermediate storage poly structures formed during fabrication thereof

The present invention provides a method and apparatus for detecting and locating a fault in an integrated circuit structure formed in one or more insulating layers deployed on a semiconductor substrate. The apparatus includes a probe tool capable of detecting a fault in the integrated circuit structure, a laser tool capable of forming an electrical connection between the integrated circuit structure and the semiconductor substrate, and a controller coupled to the probe tool and the laser tool, wherein the controller is capable of directing the laser tool to form the electrical connection between the integrated circuit structure and the semiconductor substrate in response to detecting the fault in the integrated circuit structure. The apparatus also includes a source for providing an electrical charge to the integrated circuit structure in response to detecting the fault in the integrated circuit structure and a detector for detecting an electrical charge accumulation in at least a portion of the integrated circuit structure.

Growing community of inventors

Caldwell, ID, United States of America

James E Green