Rca Inc.

Intersil Corporation

James E Gillberg

Nicholas Kucharewski

Raymond L Giordano

Robert A Dwyer

Robert J Reilly

William R Cohen

Jeffrey M Bessolo

A thermally protected power device is disclosed and includes a semiconductor package having at least five pins. One of the pins comprises a ground pin for connecting to a ground connection, and another one of the five pins comprises a power pin for connecting to a source of a temperature stable reference voltage. A field effect transistor is formed within the semiconductor package and has a source, drain and gate connected to three of the output pins and forms respective source, drain and gate pins. A parasitic bipolar transistor is formed within the package and has a base, collector and emitter. The collector is connected to the gate of the field effect transistor. A voltage divider circuit is formed within the semiconductor package and connected to the power pin, the ground pin and the base of the thermal limiting bipolar transistor for receiving a temperature stable reference voltage obtained from a temperature stable voltage source connected to the power pin, and dividing the voltage down close to the Vbe of the thermal limiting bipolar transistor. As the temperature rises within the semiconductor package, the Vbe of the thermal limiting bipolar transistor drops and switches on to pull gate voltage down and limit current passing through the field effect transistor.

Current limited, thermally protected, power device

The loss of an AC supply voltage is detected by sensing the amplitude of the AC voltage relative to the reference potential about which it periodically goes positive and negative. Whenever the amplitude of the signal is below a given threshold, a sub-threshold signal is produced and its duration is sensed. If its duration is shorter than a predetermined sampling period, the sub-threshold signal is treated as a normally occurring signal and is filtered out of the system. If its duration exceeds the predetermined sampling period, it indicates that the AC voltage has remained 'low' for too long a period of time, and an error signal is generated.

Power down sensor

A bond region is provided on an integrated circuit chip wherein the bond region has two or more sets of closely spaced conductors, each of which is electrically connected to a different point of the integrated circuit. During the manufacturing of the device, at the time of assembly of the chip into the package one end of a connector wire may, optionally, be bonded to the bond region thereby effecting a multiple connection of these different points of the integrated circuit. Such a procedure will enable a specific mode of operation of a multi-mode device.

Multiple connection bond pad for an integrated circuit device and method

Circuitry for discriminating between input signals having peak amplitudes which fall with two ranges includes two Schmitt triggers having their input terminals connected to a common circuit input terminal. The trigger points of the two Schmitt triggers overlap each other. The potential difference between the upper trigger points of the two Schmitt triggers establishes one of the input signal amplitude ranges. Signals with amplitudes greater than the upper trigger point of the higher of the two upper trigger points fall into the second of the two signal ranges. Decoder circuitry coupled to the outputs of the two Schmitt triggers determine if one or both of the Schmitt triggers is regularly responding to the input signal and thereby the relative amplitude range of the applied signal.

Detection circuitry with multiple overlapping thresholds

An input signal is applied to a first flip-flop whose output is coupled to the input of a second flip-flop. The two flip-flops are clocked, at a time t.sub.1 and at a subsequent time t.sub.2, for storing the value (SI.sub.1) of the input signal at time t.sub.1 in one flip-flop and for storing the value (SI.sub.2) of the input signal at time t.sub.2, in the other flip-flop. Logic gates coupled between the first and second flip-flops and a third, set/reset, flip-flop sense the values (SI.sub.1 and SI.sub.2) of the input signal stored by the first and second flip-flops and either: (a) set the third flip-flop to a condition indicative of the value of the input signal at times t.sub.1 and t.sub.2 if SI.sub.1 is equal to SI.sub.2 ; or (b) maintain the third flip-flop undisturbed in the state to which it was set just prior to t.sub.1 if SI.sub.1 is not equal to SI.sub.2.

Transient signal suppression circuit

A watch circuit arrangement for conserving battery power includes a feedback connection between the crystal oscillator of the watch circuit and the display voltage generator which is responsive to the crystal oscillator output to develop sufficient output voltage for the watch display. Specifically, the output of the display voltage generator, which may be a voltage multiplier, is sensed by a display voltage sensing circuit which controls the gain of the crystal oscillator. Initially, when battery power is applied to the watch circuit, the voltage multiplier has zero output voltage, which conditions the crystal oscillator to have a sufficiently high gain to start the oscillator. After several cycles of oscillator signal, the voltage multiplier output increases, which conditions the crystal oscillator to have a lower gain for reducing power consumption while sustaining oscillation.

Watch circuit with oscillator gain control

A complementary MOS input circuit not only transfers input signal swinging between conventional logic levels in a normal mode but also provides a control signal upon application of an input signal swinging outside the normal range of logic levels. This control signal is then available to be used to change selective connections in an integrated circuit to change its operating function, for example. The input circuit includes first and second complementary MOS transistors arranged like an inverter but having their gates connected to a fixed potential and having input signal potential applied to the source of the first transistor. The transistors exhibit an output signal at the interconnection between their drain electrodes which output changes state on an input swinging past the fixed potential sufficiently to render the first transistor conductive.

Circuit with dual-purpose terminal

A gated oscillator implemented with cascade-connected inverting logic circuits and resistor-capacitor timing elements generates oscillations so long as an inhibiting signal is not applied to one of the logic circuits. Means are provided to maintain potentials on the timing elements during application of inhibiting signal, which potentials are equivalent to steady-state operating potentials at the inception of a state transition. When the inhibiting signal is discontinued allowing oscillations to be generated, the initial pulse period is equal to the steady-state pulse period.

Gated oscillator

In a drive circuit having output current passing through at least one bipolar transistor, the rise and fall times of the output current are predetermined by controlling the rate of current change in the master path of a current mirror amplifier which has a separate slave path connected to supply base current for each bipolar transistor. The drain-source channel of an MOS transistor is connected to selectively supply current flow through the master path of the current mirror amplifier in one embodiment of the rate control means and the gate of the MOS transistor is connected in parallel with a capacitor to the output of a CMOS inverter to which control signals are applied. Multiple outputs are driven from a single control input in another embodiment having a single master path and multiple slave paths incorporated into the current mirror amplifier with each slave path being connected to supply base current for a separate bipolar output transistor and being coupled to the master path through a separate transmission gate in a decoder which includes a transmission gate for each slave path.

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Flemington, NJ, United States of America

James E Gillberg