Integrated Device Technology, Inc.

James E Fox, Jr

David L Campbell

An output driver including pull-up and pull-down output transistors is formed in a silicon substrate. The source and the drain of the pull-up output transistor are formed in a common bulk region of the substrate. A bulk potential control circuit for controlling the voltage of the bulk region, a resistive element and a gate drive control circuit are also formed in the silicon substrate. A layer of interconnect formed over a top surface of the silicon substrate may selectively couple into the output driver circuit one or more of the resistive element between a source of the pull-down output transistor and a reference voltage source, the bulk potential control circuit to control the voltage of the bulk region of the silicon substrate, and the gate drive control circuit to control the rate of change of voltage on the gate of the pull-down transistor as a function of the voltage on this gate.

Method and structure for selectively coupling a resistive element, a

An output driver circuit capable of driving its data output terminal to a digital logic level high, capable of driving its data output terminal to a digital logic level low, and capable of tristating its data output terminal has an output stage comprising a pullup field effect transistor (FET) and a like-polarity pulldown FET. The two pullup and pulldown FETs are coupled in series between two voltage supply lines. In one aspect of the invention, the output driver comprises a charge rate control circuit which charges the gate of the pulldown FET when the pulldown FET is to be turned on so that the voltage on the gate increases at a first rapid rate and then increases at a second slower rate after the pulldown FET begins to conduct current. In another aspect of the invention, a resistive element is provided between the source of the pulldown FET and a ground voltage supply line. In another aspect of the invention, the output driver circuit comprises a bulk potential control circuit which changes the voltage of the semiconductor bulk in which the pullup FET is disposed. Accordingly, bounce on the voltage supply lines is minimized, propagation delay through the output driver is minimized, and the output driver is suitable for use in applications requiring the handling of live insertion.

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San Jose, CA, United States of America

James E Fox, Jr