Intel Corporation

James E Breisch

Jung S Kang

Mark A Beiley

Kevin M Connolly

Akira Kakizawa

Berni W Landau

Cory E Weber

Shaofeng Yu

Chee-Yee Chung

Zong-Fu Li

Alex Waizman

Teong Guan Yew

Joseph W Parks, Jr

Jack W Heller

Tonia G Morris

Structures and methods are provided for dual referenced microstrip structures having low reference discontinuities between a microstrip trace referenced to a primary reference plane as compared to a microstrip trace referenced to a secondary reference plane. A method, according to one embodiment of the invention, includes the calculation of a first characteristic impedance of the dual referenced microstrip transmission line referenced to a primary reference layer, the calculation of a second characteristic impedance of the dual referenced microstrip transmission line referenced to a secondary reference layer, the calculation of an absolute value of a difference between the first and the second characteristic impedance, the comparison of the absolute value of the difference to a predetermined threshold value, and if the absolute value of the difference is greater than the predetermined threshold value, then a physical parameter associated with the characteristic impedance between the primary and secondary reference layers may be varied until the difference is reduced to less than the predetermined threshold. A structure, according to one embodiment of the invention includes a microstrip transmission line, a first conductive plane, a first dielectric layer provided between the microstrip transmission line and the first conductive plane, a second conductive plane, and a second dielectric layer provided between the first conductive plane and the second conductive plane.

Dual referenced microstrip

A circuit includes a capacitor formed with a dielectric including the dielectric encasing elements of the circuit. A detector detects changes in the capacitance of the capacitor.

Method and apparatus to detect circuit tampering

A mechanism is provided for delivering power to an on-die component (such as a buffer circuit). This may include a package unit having a low frequency delivery path and a high frequency delivery path and a die having the on-die component and a capacitive device each coupled in parallel between a first node and a second node. The die may further include a low frequency reception path and a high frequency reception path. The low frequency reception path may couple to the low frequency delivery path on the package unit and to the first node. The high frequency reception path may couple to the high frequency delivery path on the package unit and to the first node. The high frequency reception path may include a damping resistor.

Multi-frequency power delivery system

An imaging system includes an array of pixel sensors and a mode control circuit. The array of pixel sensors is adapted to furnish logarithmically encoded indications of light intensities during a first mode and furnish linearly encoded indications of the light intensities during a second mode. The mode control circuit is adapted to selectively place the array in one of the first and second modes. The imaging system may include more than one array, and the mode control circuit may configure one of the arrays. The imaging system may include a camera, for example, that includes the array(s) and mode control circuit.

Imaging system having multiple image capture modes

Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.

Reduced leakage trench isolation

Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.

What is disclosed is a single integrated circuit having an image sensor for outputting signals representative of input light; a programmable non-volatile memory for storing defective pixel location information; a controller unit for interfacing with the programmable non-volatile memory and accessing the defective pixel location information; and a input/output port for communicating with control and post-processing circuitry.

CMOS imaging device with integrated defective pixel correction circuitry

A circuit includes a first oscillator having transistors to produce a first signal with random variations resulting from device channel resistance of the transistors.

Method and apparatus to produce a random bit sequence

An embodiment of the invention is directed to a semiconductor photodiode made of a number of gate islands being spaced from each other and electrically insulated from each other by spacers. The spacers are formed above a p-n junction of the photodiode. The incident light is detected after it passes through the spacers and into a photosensitive region of the photodiode. The photodiode can be built using conventional metal oxide semiconductor (MOS) processes of the polysilicon-silicided gate or self-aligned types that use a lower doped drain (LDD) structure, without requiring an additional mask step that prevents the formation of the opaque silicide above the photosensitive semiconductor regions.

Photodiode having transparent insulating film around gate islands above P-N junction

A single integrated circuit having an image sensor for outputting signals representative of input light; a programmable non-volatile memory for storing security information; a controller unit for interfacing with the programmable non-volatile memory and accessing the security information; and an input/output port for communicating with a control and post-processing circuit.

Growing community of inventors

Chandler, AZ, United States of America

James E Breisch