Advanced Micro Devices Corporation

James E Bowles

Dale E Gulick

Robert O'Brien

John G Bartkowiak

Munehiro Yoshikawa

Shin Saito

Joseph W Peterson

Hiroshi Matsubara

Arthur Benjamin Oliver

Mark Luedtke

Robert W O'Dell

Bruce R Allen

A memory system for reducing cache snooping overhead for a two level cache system with multiple bus masters, has a level 2 cache connected to a main memory and a level 1 cache connected to a bus master. Each bus master has one level 1 cache assigned to it. A shared level 2 cache is connected to each of the level 1 caches. The level 2 cache has an inclusion field for each storage location within the level 2 cache. The inclusion field indicates if information held in a storage location associated with the inclusion field is contained in any of the level 1 caches connected to the shared level 2 cache, and whether that data has been modified. If there is a cache hit in the level 2 cache, the level 2 cache determines from the inclusion field that corresponds to the cache hit if the tag-address corresponding to the memory access of the bus master also resides in a level 1 cache assigned to a different bus master than the one that made the memory access, and if the corresponding data has been modified. If so, the shared level 2 cache obtains the data from the level 1 cache assigned to the other bus master, and that data is read into the level 2 cache. The data is then read from the shared level 2 cache into the level 1 cache assigned to the bus master that initiated the memory access.

Reducing cache snooping overhead in a multilevel cache system with

A memory system for reducing cache snooping overhead for a two level cache system with multiple bus masters, wherein the level 2 cache is connected to a main memory and wherein the level 1 cache is connected to a bus master. For each bus master, there is one level 1 cache assigned to it, and there is a shared level 2 cache that each of the level 1 caches are connected to. The level 2 cache has an inclusion field for each storage location within the level 2 cache. The inclusion field indicates if information held in a storage location associated with the inclusion field is contained in any of the level 1 caches connected to the shared level 2 cache. If there is a cache hit in the level 2 cache, the level 2 cache determines from the inclusion field that corresponds to the cache hit if the tag-address corresponding to the memory access of the bus master also resides in a level 1 cache assigned to a different bus master than the one that made the memory access. If so, the shared level 2 cache obtains the data from the level 1 cache assigned to the other bus master, and that data is read into the level 2 cache. The data is then read from the shared level 2 cache into the level 1 cache assigned to the bus master that initiated the memory access.

A weak pull-up disable method and mechanism therefor for use in association with a microcontroller incorporated in an integrated circuit. The weak pull-up disable mechanism is incorporated in the integrated circuit containing the microcontroller. The mechanism disables the weak pull-ups of I/O buffers of the microcontroller. The weak pull-ups serve to pull the voltage of the associated ports high. By so disabling the weak pull-ups, the need for a driver to sink the current when in input mode is eliminated. Elimination of the need for an external driver due to the weak pull-up disable mechanism reduces power consumption by the integrated circuit.

Method and mechanism of weak pull-up for use with a microcontroller in

An integrated circuit especially suitable for incorporation into the base and handset units of a cordless telephone integrates the speech, control channels, and microcontroller portions of a modem, and the man-machine interface functions of a cordless telephone. The integrated circuit includes one or more of a number of aspects including an in-circuit emulation mechanism, a simplified keypad reporting mechanism, advanced noise suppression mechanisms, a low power emergency mode mechanism, a low cost serial control bus, a port pin interrupt mechanism, advanced power saving mechanisms, spectral measurement test mode means, a novel shut down mechanism, and a pull-up disabling mechanism.

Integrated circuit and cordless telephone using the integrated circuit

An apparatus for enabling an interrupt under certain hardware condition even though the interrupt has been masked by software, includes structure for indicating a software condition, structure for indicating a hardware condition, and structure, that is responsive to both aforementioned structures, for generating an interrupt in response to the assertion of an interrupt request signal.

Apparatus and method for disabling interrupt masks in processors or the

A processing system of the type having a processor which accesses external memory for data and/or instructions which includes an improved external memory access control system for rendering the external memory enable time durations independent from the number of external memory accesses per unit of time for reducing power consumption of the processing system. The control system includes a selectably programmable clock for providing a clock signal of one of at least two speeds for determining the external memory access rate. The control system also includes enable duration control structure coupled to the selectably programmable clock. The enable duration control structure is arranged to enable the external memory for time durations during each memory access which are independent from the external memory access rate. Further, the enable duration control structure includes substructure for changing the duty cycle of external memory enable time duration control signals based upon the selected clock speed.

External memory access control for a processing system

A bus interface for use in a processing system of the type including a processor such as a microprocessor or a microcontroller permits the processor to access either a non-multiplexed peripheral interface or a multiplexed peripheral interface, wherein the non-multiplexed peripheral interface includes an upper address input, a lower address input, and a data port, wherein the multiplexed peripheral interface includes a multiplexed address and data port, and wherein the processing device includes an internal upper address bus, an internal lower address bus, and an internal data bus. The bus interface includes an external upper address bus coupled to the upper address input, an external lower address bus coupled to the lower address input, and an external address/data bus coupled to the data port and to the multiplexed address and data port. The bus interface further includes bus interface circuit for coupling during an access to the non-multiplexed peripheral interface by the processor, the internal upper address bus to the external upper address bus, the internal lower address bus to the external lower address bus, and the internal data bus to the external address/data bus. During an access to the multiplexed peripheral interface by the processor, the bus interface circuit couples first the internal lower address bus to the external address/data bus and thereafter, the internal data bus to the external address/data bus.

Microprocessor arranged to access a non-multiplexed interface or a

In a watchdog timer, the selected codes identifying the format of a watchdog timer algorithm, such as the intervals within which a watchdog timer status must be issued by the host processor, are supplied as hardwired preset codes in programmable fuse or read only memory cells that are adapted to be programmed, but are immune from ESD, power glitches and errant software. A programmable code indicating a programmable time interval is also stored in a register protected from errant software when the watchdog timer is enabled. A selector receives the preset code and the programmable code and selects an output code indicating the time interval within which the watchdog timer must be reset by a processor status signal. The selector can be programmed to select only the preset code by supplying a selector control signal through an element that is immune from electrostatic discharge, power glitches and errant software. Also, a code fixing the watchdog timer in an on state can be supplied with ESD-immune cells. The watchdog timer employs a keyed sequence for the watchdog timer status signal.

Reliable watchdog timer

A testing circuit for testing field-effect transistors of, for example, a random access memory includes weak N-channel pull-down field-effect transistors and weak P-channel pull-up field-effect transistors for testing field-effect transistors of opposite type to be tested. The weak field-effect transistors are placed in series with the opposite type of field-effect transistors. When the series coupled field-effect transistors are turned on, the voltage at the common node of the field-effect transistors is sensed to determine whether the common node is pulled-up or pulled-down in potential to indicate whether a field-effect transistor under test is functional.

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Austin, TX, United States of America

James E Bowles