Intel Corporation

Seiko Epson Corporation

James E Akiyama

Debendra Das Sharma

David J Harriman

Robert G Blankenship

Mahesh U Wagh

Mark B Rosenbluth

Jasmin Ajanovic

Scott Dion Rodgers

Anil Vasudevan

Prashant Sethi

Ilan Pardo

Sridhar Muthrasanallur

Ajay V Bhatt

Eran Tamari

Doron Shamia

Peter J Barry

Eliezer Weissmann

Ohad Falik

Abraham Mendelson

Douglas L Gabel

Peter D MacWilliams

Avi Mendelson

William H Clifford

Satish Ramanathan

Kuljit Singh Bains

Avi (Abraham) Mendelson

Murali Ramadoss

Randy B Osborne

John S Howard

Todd M Witter

Gary Smith

Zhengmin Li

Venkataramani Gopalakrishnan

Srikanth Kambhatla

Duane G Quiet

Gary K Smith

Sean Dardis

Ravi Nagaraj

Dmitriy Berchanskiy

Anoop Parchuru

Paul M Brown

Everardo D Ruiz

Tom Willis

Ohad Fallk

Ellezer Weissmann

Avi (Arraham) Mendelson

Aniruddha Kunda

Daniel Paul Wilde

Shrestha Sinha

Ravishankar Subramanian

Jose A Meza Arellano

Kevin Southern

Douglas Gabel

William Clifford

Peter Macwilliams

Paul Brown

Methods, systems and apparatuses may provide for technology to receive a first video data stream from a first graphics display engine via a first video data channel, receive a second video data stream from a second graphics display engine via a second video data channel, and switch a video output from the first video data stream to the second video data stream based on a switch command to accompany the second video data stream.

Runtime switchable graphics with a smart multiplexer

Embodiments are directed toward apparatuses, systems, and methods to implement policies for dynamically switching between an integrated graphics mode and a discrete graphics mode for providing a display signal to an external USB Type-C port. Some embodiments include a controller configured to provide signals to a first multiplexer and to a second multiplexer, and based on a platform policy, control the at least first or the second multiplexer to dynamically switch to the first graphics mode to output signals received from an integrated graphics controller to the external USB Type-C port or to switch to the second graphics mode to output signals received from a discrete graphics controller to the external USB Type-C port. Other embodiments may be described and/or claimed.

Apparatuses, systems, and methods for dynamically switching graphics modes for providing a display signal

Examples described herein relate to a graphics processing system that includes one or more integrated graphics systems and one or more discrete graphics systems. In some examples, an operating system (OS) or other software supports switching between image display data being provided from either an integrated graphics system or a discrete graphics system by configuring a multiplexer at runtime to output image data to a display. In some examples, a multiplexer is not used and interface supported messages are used to transfer image data from an integrated graphics system to a discrete graphics system and the discrete graphics system generates and outputs image data to a display. In some examples, interface supported messages are used to transfer image data from a discrete graphics system to an integrated graphics system and the integrated graphics system uses an overlay process to generate a composite image for output to a display.

Switchable image source in a hybrid graphics systems

Aspects of the embodiments are directed to a ThunderBolt (TBT) input/output (I/O) controller apparatus. The TBT I/O controller apparatus can include an output port to receive a connection to a display device; a multiplexer coupled to the output port; a first input port coupled to the multiplexer; a second input port coupled to the multiplexer; a memory element to store graphics preference data; and TBT firmware (FW). The TBT FW can detect a connected device at the input port; determine a graphics processor for the connected device based on the graphics preference data; and logically connect the connected device to one of the first input port or the second input port through the multiplexer based on the determined graphics processor.

Method, apparatus, system for thunderbolt-based display topology for dual graphics systems

Systems, apparatuses and methods may provide for technology that based on information from a connected display device, forms a determination whether to connect a discrete graphics processor or an integrated graphics processor to the connected display device, the information corresponding to whether the connected display device is to be driven by the integrated graphics processor or the discrete graphics processor.

Switchable hybrid graphics

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Atomic operations in PCI express

Transaction layer packet formatting

PCI express transaction descriptor

Transaction re-ordering

Prefectching in PCI express

An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.

Accessing memory using multi-tiling

In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Memory controller interface for micro-tiled memory access

Atomic operations

PCI express enhancements and extensions

Growing community of inventors

Beaverton, OR, United States of America

James E Akiyama