Acacia Communications, Inc.

Emulex Design & Manufacturing Corporation

Other

Conexant Systems, Inc.

James Duda

Jon Stahl

Pierre A Humblet

Michael Sluyski

Sudhir Srinivasan

Glenn A Dearth

Nathan J Dohm

Carl John Lindeborg

Michael Joseph Schaffstein

Robin Lee Brown

George M Jacobs

Kevin Hinchey

Andre M Hassan

Robert Swope Fleming

A method, system, and apparatus for determining delay between clocks, in response to a trigger event, buffering DSP symbol information in a symbol capture buffer; wherein the amount of DSP symbol information buffered corresponds to the amount of symbols captured during a buffer storage interval; and extracting a synchronization packet from the symbol capture buffer.

Clock synchronization

A system, method, and apparatus enabling synchronous and asynchronous data sources to be demapped from an oFrame container using a generic mapping system.

System, method, and apparatus for mapping synchronous and asynchronous data

A system, apparatus, and method for an optical grooming network; wherein a set of switches form an optical grooming interconnection system where each switch is communicatively coupled to each other switch; a set of clients; where each switch of the set of switches is communicatively coupled to a client of the clients; wherein each client receiver is enabled to communicate through the set of switches to any client or modem; and a set of coherent optical modems; wherein each coherent optical modem is communicatively coupled to a switch of the set of switches; wherein each client of the clients is able to communicate through the set of switches to every coherent optical modem of the set of coherent optical modems, and each coherent optical modem in the set of coherent optical modems can communicate to every coherent optical modem of the set of coherent optical modems.

Optical grooming interconnection network

A method, system, and apparatus for transmitting information over an coherent optical link comprising enabling synchronous and asynchronous data sources to be mapped together into a single payload using a generic mapping system which performs decoupling of a clock from each data source, and mapping data from each data source into a tributary of an oFrame.

A system for booting a processor from NAND flash, comprising a NAND agnostic boot controller and a NAND flash device, wherein the NAND flash device further comprises a boot wrapper storing boot code in a predetermined format.

Processor NAND flash boot system and method

In a digital data processing system having a memory component, a structure and method for managing available memory resources. Free pointers to respective free memory blocks are stored in memory blocks maintained as a linked list. In a system having a hierarchically-organized memory component, a small number of the free pointers are maintained at a relatively higher performance level of the memory and the balance of the free pointers are maintained at a relatively lower performance level of the memory.

Structure and method for managing available memory resources

In a memory controller for use with a DDR SDRAM, an apparatus improves the immunity of the controller to noise glitches on the DQS signal provided by the DDR SDRAM during READ operations. A method adjusts the noise immunity provided by the apparatus. In particular DQS quality circuits frame the DQS signal for a predetermined portion of the READ operation.

Method and apparatus for improving noise immunity in a DDR SDRAM system

A direct memory access controller is provided which utilizes a single dedicated controller to control all or substantially all memory accesses in a computer system, both memory-to-memory accesses within the system and transfers between system memory and various system peripherals. At least portions of the controller are time shared by various channels, each channel performing data transfers in a selected direction between a system memory component and a second component which may be a peripheral, another memory component or the like. An arbiter is provided as part of the controller for determining the channel using shared resources at any given time. Where one of the peripherals is a variable length packetized data source, multiple subchannels may be provided for transfers of data for such source into system memory, each such subehannel being for transfers to buffers of different size. Efficient memory utilization is achieved by determining the size of an incoming variable length packet and having the transfer performed through the channel servicing the smallest available buffer in which incoming variable length packetized data will fit.

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Waltham, MA, United States of America

James Duda