Cirrus Logic Inc.

Skyworks Solutions, Inc.

Silicon Labs Cp, Inc.

Silicon Laboratories Inc.

Crystal Semiconductor Corporation

James Dub Austin

Kenneth Wilson Fernald

Sean Anthony Lofthouse

Douglas S Piasecki

Douglas R Holberg

Douglas D Gephardt

Thomas Saroshan David

James David Barnette

Scott Thomas Haban

Gregory Allen North

David M Pietruszynski

Brian G Kirkland

Brian Christopher Kircher

A calibration operation determines a resistance of a sense resistor in a POE system. A voltage measurement is taken with a first current flowing through the sense resistor. A second voltage measurement is taken with a second current flowing through the resistor. A resistance value of the sense resistor is determined based on a voltage difference between the first and second voltage measurements and a current difference between the first current and the second currents.

Calibration of the external resistance value in the power sourcing equipment of a power over ethernet system

Calibration of the external resistance value in the power sourcing equipment of a POE system

A fault tolerant communication protocol transmits information across a communication channel from a transmitting device to a receiving device. The receiving device echoes back a copy of the transmitted information to the transmitting device. The transmitting device sends a first valid signal across the communication channel if the echoed information matches the transmitted information. The receiving device sends a second valid signal across the communication channel responsive to the first valid signal. The transmitting device stops sending of the first valid signal responsive to the second valid signal and the receiving device stops sending the second valid signal responsive to determining the first device has stopped sending the first valid signal. The receiving device can then update its state based on a successful transfer.

Fault tolerant communication channel

Electrostatic discharge (ESD) clamp using output driver. An electrostatic discharge (ESD) protection device for an output driver having a p-channel transistor and n-transistor pair connected between a power supply terminal and ground for driving an input/output pad therefrom. An ESD event detector is provided for detecting an ESD event on the pad. A drive circuit drives the n-channel and p-channel drive transistors in response to receiving a logic control signal to either drive the pad from the supply terminal or to sink the pad to ground. ESD protection logic circuitry is provided to cause both the p-channel and n-channel transistors to turn on when the ESD event detector detects an ESD event, the ESD protection circuitry disposed forward of the drive circuit such that the ESD protection logic circuitry operates independent of the state of the drive circuit.

Electrostatic discharge (ESD) clamp using output driver

Method and apparatus for combining outputs of multiple DACs for increased bit resolution. A method for providing an increased bit resolution to a data converter operable to convert digital information to analog values. A first current Digital-to-Analog (IDAC) converter is controlled to provide current to a first output node, the first IDAC having a first current step size associated with the Least Significant Bit (LSB) thereof. A second IDAC is controlled to provide current to the first output node, the second IDAC having a second current step size associated with the LSB thereof that is smaller than the first current step size. The combination of the first and second IDACs increases the bit resolution of the first IDAC when driving the first output node with the second IDAC.

Method and apparatus for combining outputs of multiple DACs for increased bit resolution

A static, low-power differential sense amplifier (DSA) and method includes operation of cross-linked channels having complementary differential nodes separated from ground by corresponding parallel-transistor pairs. The DSA output channels have complementary output nodes separated from ground by corresponding parallel-transistor pairs. The DSA further includes logic gates to produce a sense amplifier output. Each logic gate is driven by a corresponding complementary differential node and an opposite complimentary output node. The DSA includes transistors activating a done line under control of the complementary differential nodes.

Bitline amplifier having improved response

An audio information processing subsystem 200 is disclosed which includes a stream processor 100 for simultaneously processing multiple streams of audio data. Processing subsystem 200 also includes a program memory 202 coupled to stream processor 100 for storing instructions for controlling processing system 200 and a data memory 203/204 also coupled to stream processor 100. Additionally, a direct memory access circuitry 208 is provided for controlling direct memory accesses to a selected one of program memory 202 and data memory 203/204.

Circuits, system, and methods for processing multiple data streams

Static low-power differential sense amplifier circuits, systems and

An output driver is provided for operating in a primary power supply environment to drive an output system that can have voltages associated therewith that are higher than the primary power supply level. The driver includes a pull-down N-channel (34) and a pull-up P-channel transistor (44). An output node (40) is driven by the transistor (34) and (44). An N-channel protection device (38) is disposed between node (40) and transistor (34) and an N-channel transistor (48) is disposed between node (40) and transistor (44). Transistor (38) has the gate thereof biased to the primary supply voltage level and the transistor (48) has the gate thereof biased to a voltage slightly above the primary supply voltage level. This configuration allows a common control signal varying up to the primary power supply level utilized to drive both transistors (34) and (44) and also to remove the requirement that any of the wells associated with the driver transistors be biased to a voltage above the primary supply voltage level, to prevent current being conducted to the primary supply from the output node during a high voltage condition or for the voltage of any of the transistors to exceed a voltage slightly above that of the primary voltage supply level.

Growing community of inventors

Austin, TX, United States of America

James Dub Austin