International Business Machines Corporation

Globalfoundries Inc.

James Douglas Warnock

Dieter F Wendel

Leon Jacob Sigal

Ayan Datta

Sang Hoo Dhong

Sumitha George

Charudhattan Nagarajan

Vijay K Ankenapalli

Joel Abraham Silberman

Osamu Takahashi

Jeffrey Paul Soreff

William Vincent Huott

Peter Juergen Klim

Christopher McCall Durham

Owen Chiang

Jente Benedict Kuang

Hung Cai Ngo

Phillip John Restle

Stephen Gerard Shuma

Michael H Wood

Vasant B Rao

Effendi Leobandung

Tak H Ning

Kerim Kalafala

Steven Michael Douskey

Mary Prilotski Kusko

K Paul Muller

Philip Joseph Oldiges

Gregory Gower Freeman

Ethan Harrison Cannon

Sam Gat-Shang Chu

Sachin Gupta

Siyuranga O Koswatta

Sridhar H Rangarajan

Christos Vezyrtzis

Ricardo H Nigaglioni

Joachim Gerhard Clabes

Hemlata Gupta

Aj KleinOsowski

J Campbell Scott

Nagashyamala R Dhanwada

Raghu Gaurav GopalaKrishnaSetty

Erwin Behnen

Raghu G GopalaKrishnaSetty

Manish Verma

Hagen Schmidt

Naiju K Abdul

Suriya T Skariah

Hari Krishnan Rajeev

Daniel J Poindexter

Jennifer E Basile

Ankit N Kagliwal

James E Sundquist

Jeremy J Leitzen

Michael Normand Goulet

Robert N Krentler

Ankur Shukla

Subramanian Srikanteswara Iyer

David James Hathaway

Chandramouli Visweswariah

Gregory John Uhlmann

Chin Ngai Sze

Bruce Martin Fleischer

Ruchir Puri

Brian William Curran

David E Lackey

Tobias Webel

Arun Joseph

Debjit Sinha

Klaus D Beyer

Paul Stephen McLaughlin

Haifeng Qian

Mark A Jaso

Manjul Bhushan

Preetham M Lobo

Thomas Edward Rosser

Richard Frank Rizzolo

Scott R Stiffler

George E Smith, Iii

Eric Jason Fluhr

Sungjae Lee

Patrick M Williams

Louis Bernard Bushard

Jason David Morsey

Michael R Scheuermann

Arjen Alexander Mets

David Wells Winston

Steven Eugene Washburn

Neil R Vanderschaaf

William W Dungan

Sang Y Lee

David Kadzov

Scott Taylor

Johnny J Leblanc

Richard A Wachnick

Wendel Dieter

George E Iii Smith

Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.

Operating pulsed latches on a variable power supply

A method and system for improving the performance of a computer in identifying and mitigating electromigration violations of a semiconductor device. A set of library gates is obtained and parasitic layout extraction is performed for each gate in the set of library gates to generate an extracted netlist. One or more passes of an electromigration analysis of the extracted netlist are performed to characterize each gate over a set of input parameters and to generate a maximum slew rate (MAX_SLEW) table and a maximum capacitance (MAX_CAP) table.

Characterizing and simulating library gates to enable identification and elimination of electromigration violations in semiconductor chips

A computer-implemented method includes receiving a text description of a logic circuit design, reading a plurality of circuit priority indicator values, synthesizing a logic circuit design based, at least in part, on those circuit priority indicator values, and fabricating logic circuits using the synthesized logic circuit design. A corresponding computer program product and computer system are also disclosed herein.

Priority based circuit synthesis

Techniques for determining the quality of a clock signal are provided. In one example, a method can comprise comparing, by a sensory circuitry of a system, a first output of a first sensor and a second output of a second sensor. The first output and the second output can be based on a parameter of a clock signal. Further, in some embodiments, the first sensor and the second sensor can be local clock buffers. The method can also comprise determining, by a controller of the system, a quality of the clock signal based on the comparing of the first output and the second output.

Determining clock signal quality using a plurality of sensors

A system and method to perform an integrated circuit design involves selecting a net among a plurality of nets of the integrated circuit design as a victim net. Each net connects a pair of nodes of the integrated circuit design and each node represents a logic element of the integrated circuit design. The method also includes determining aggressor nets among the plurality of nets for the victim net and determining a corresponding weight value for each of the aggressor nets and, for each of the aggressor nets, multiplying the coupled noise originating from the aggressor net with the corresponding weight value to obtain a weighted coupled noise value. A cumulative coupled noise value is obtained for the victim net as a sum of the weighted coupled noise values associated with each of the aggressor nets. A result of the integrated circuit design is provided for fabrication into an integrated circuit.

Pessimism reduction in cross-talk noise determination used in integrated circuit design

A method, system, and compute program product use a generalized macro or a generalized macro timing abstract for timing analysis in a specific timing context. The method includes setting up a timer, and determining a divide ratio of each external clock divider of one or more external clock dividers associated with the generalized macro or the generalized macro timing abstract programmatically as a function of another value. The method also includes performing the timing analysis using the divide ratios of the one or more external clock dividers. Obtaining a physical implementation of an integrated circuit is based on the timing analysis.

Programmable clock division methodology with in-context frequency checking

A latch circuit having a master latch and a slave latch includes a device used to short either the master latch or the slave latch. The device includes a transistor and a global control used to assert a signal, and is positioned to short an inverter of the master latch or the slave latch. When the signal is asserted by the global control, the inverter is shorted such that the output value of the inverter is the same as the input value. The assertion of the signal is facilitated by another device connected to the master latch and the slave latch that includes the global control and a transistor.

Debugging scan latch circuits using flip devices

A method includes receiving a circuit design comprising an input scan chain comprising a plurality of latches connected by one or more scan connections, dividing the plurality of latches into one or more clusters, determining a number of scan controls for each cluster, placing the determined scan controls in selected locations; and adjusting the scan connections based on the scan control location. A corresponding computer system and computer program product are also disclosed.

Adjusting scan connections based on scan control locations

A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.

On-chip sensor for monitoring active circuits on integrated circuit (IC) chips

A computer-implemented method includes receiving, with one or more processors, a text-based description of a logic circuit comprising a plurality of logic sub-circuits, determining within the text-based description, with one or more processors, a set of circuit priority indicators for a corresponding set of the logic sub-circuits, and synthesizing, with one or more processors, the logic circuit according to the set of circuit priority indicators to provide a synthesized circuit description. A corresponding computer program product and computer system are also disclosed herein.

A standard cell for use within an integrated circuit can be partially personalized by local wiring. The standard cell can include a set of transistors, each having a fixed size and position within an established standard cell perimeter. The set of transistors can be partially interconnected to a set of local nodes by local wiring. Customization ports can be arranged on a global wiring layer and electrically connected to the set of local nodes. A set of blockage in shapes can be arranged to identify, on a global wiring layer, areas reserved for personalization wiring. Personalization wiring can be configured to complete the personalization of the standard cell by electrically interconnecting, on the global wiring layer, some of the set of customization ports.

Programmable integrated circuit standard cell

A system and method for enabling the estimation and mitigation of self-heating in chip designs at a much earlier stage in a design flow. The system and method provides unique characterization of each standard cell in a library for its effective thermal resistance based on the topology and layout of the cell, and brings this per standard cell instance based delta-T to be available for the timing closure tools when completing a synthesized design. Thus, at the timing closure process, the generated design is free of self heating violations. The method computes a unique thermal resistance characterization on per standard cell manner&#x2014;based on the topology, function and layout of the standard cell, and uses that to compute the deltaT per instance of the design. This information is presented to a violation mitigation tool which changes the power levels of the cells, logic function to mitigate the self heating violations.

Early analysis and mitigation of self-heating in design flows

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Somers, NY, United States of America

James Douglas Warnock